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Despite all prophecies of its end, silicon-based microelectronics still follows Moore's Law and continues to develop rapidly. However, the inherent physical limits will eventually be reached. Carbon nanotubes offer the potential for further miniaturization as long as it is possible to selectively deposit them with defined properties.  相似文献   
2.
The extraordinary characteristics of carbon nanotubes make them a promising candidate for applications in microelectronics. Catalyst-mediated chemical vapor deposition growth is very well suited for selective in-situ growth of nanotubes compatible with the requirements of microelectronics technology. This deposition method can be exploited for carbon nanotube vias. Semiconducting single-walled tubes can be successfully operated as carbon nanotube field effect transistors (CNTFET). A simulation of an ideal CNTFET is presented and compared with the requirements of the ITRS roadmap. Finally, we compare an upgraded CNTFET with the most advanced silicon metal oxide semiconductor field effect transistors and discuss integration issues.  相似文献   
3.
Abstract

A novel AND-type ferroelectric field effect transistor memory concept for solid state mass storage applications is described. Disturbance problems caused by disturbance pulses between adjacent memory cells are prevented by device improvements and by choosing appropriate programming and read voltages.

The memory array presented here uses global source lines each of which is connected to its own sense amplifier. Disturbance free and fully functional operation of the memory concept has been demonstrated by circuit simulations. The results of the simulations yield a data access time comparable to DRAMs.  相似文献   
4.
Carbon nanotube field-effect transistors with sub-20 nm long channels and on/off current ratios of >10(6) are demonstrated. Individual single-walled carbon nanotubes with diameters ranging from 0.7 to 1.1 nm grown from structured catalytic islands using chemical vapor deposition at 700 degrees C form the channels. Electron beam lithography and a combination of HSQ, calix[6]arene, and PMMA e-beam resists were used to structure the short channels and source and drain regions. The nanotube transistors display on-currents in excess of 15 microA for drain-source biases of only 0.4 V.  相似文献   
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