The relevance of fT and fmax for the speed ofa bipolar CE amplifier stage

Expressions relating the bandwidth of a common-emitter (CE) amplifier stage and the small-signal CML gate delay time to directly measurable transistor parameters, such as f_T, f_max, and input bandwidth f_υ, are presented. They are valid for an arbitrary division of the base resistance and base-collector depletion capacitance into internal and external components. No resistance measurements are needed. It is shown that the transistor input bandwidth f_υ is an important figure of merit for the speed of a CE stage. Under a given bias condition, f_υ is determined by the base resistance and the cut-off frequency. In most cases the value of the maximum oscillation frequency f_max is only of minor importance. It would therefore be more meaningful to present besides f_T also f_υ instead of f_max as a figure of merit for transistors for high-speed, low-power analog and digital circuits     

A new analytical model for the thermal resistance of deep-trench bipolar transistors

A new analytical model for the thermal resistance, temperature profile, and heat flow of deep-trench isolated (DTI) transistors is presented by taking the finite heat flow through the trenches into account. The new model is able to distinguish between the different contributions to the thermal resistance of the DTI structure and allows identification of the most dominant component. A detailed analysis of the substrate contribution shows that the substrate thermal resistance is overestimated in existing models. Results are compared with experimental data as well as numerical simulations and show a good agreement. The model can be used for process optimization and in a circuit simulator.     

A new recombination model for device simulation including tunneling

A recombination model for device simulation that includes both trap-assisted tunneling (under forward and reverse bias) and band-to-band tunneling (Zener tunneling) is presented. The model is formulated in terms of analytical functions of local variables, which makes it easy to implement in a numerical device simulator. The trap-assisted tunneling effect is described by an expression that for weak electric fields reduces to the conventional Shockley-Read-Hall (SRH) expression for recombination via traps. Compared to the conventional SRH expression, the model has one extra physical parameter, the effective mass m*. For m*=0.25 m₀ the model correctly describes the experimental observations associated with tunneling. The band-to-band tunneling contribution is found to be important at room temperature for electric fields larger than 7×10⁵ V/cm. For dopant concentrations above 5×10¹⁷ cm^-3 or, equivalently, for breakdown voltages below approximately 5 V, the reverse characteristics are dominated by band-to-band tunneling     

A Quantum–Mechanical View on the Capacitance of a Silicon p-n Junction

We have calculated the capacitance of a silicon p-n junction from a self-consistent solution to the effective-mass Schroumldinger and Poisson equations. Although the p-n product and the charge distribution deviate strongly from the semiclassical calculations, the quantum mechanically calculated capacitance of the silicon p-n junction differs only weakly from the semiclassical result. We show that the deviation from the semiclassical result can be approximated as band-gap narrowing in the quasi-neutral regions due to the exchange-energy term in the effective-mass Schroumldinger equation     

Transient Characteristics of the Reset Programming of a Phase-Change Line Cell and the Effect of the Reset Parameters on the Obtained State

In this paper, we investigate the effect of the reset-pulse parameters of a phase-change memory line cell on the electrical cell properties. By means of electrothermal finite-element simulations and measurements, the characteristics of the reset state (resistance after switching, threshold voltage, and stability of the state) are related to the physical parameters during reset switching (the temporal and spatial distribution of the temperature during switching, the evolution of the melting and molten phases, and the time that the line is molten). From a device point of view, we emphasize the following aspects: 1) Due to good thermal isolation, the line cell can be reset using a 5-ns short current pulse of limited amplitude; 2) longer pulsewidths allow lower reset current amplitudes due to the gradual heating of surrounding dielectric; 3) the reset resistance has no direct relation with the threshold voltage but is strongly related to the number of reset pulses applied to the cell; and 4) shorter pulsewidths allow extended endurance lifetimes.     

Intermodulation distortion of a bipolar common-emitter amplifier with arbitrary emitter impedance and input matching network

In this paper, concise formulas for the intermodulation distortion of a bipolar common-emitter amplifier stage with arbitrary emitter impedance and input matching network are presented. These expressions provide quantitative insight in the influence of transistor properties, emitter degeneration and input power matching on distortion. Only a small set of measurable transistor parameters is needed. As examples, IIP3 is calculated for transistor only, transistor with emitter inductance, and transistor with emitter inductance and input matching circuit. Two transistors are compared: a double-poly Si transistor and a SiGe transistor in a similar process. A good agreement between analytical and numerical results is obtained.     

Analyses and design of bias circuits tolerating output voltages above BV/sub CEO/

Due to the inevitable tradeoff between speed and breakdown voltage, the spectacular speed improvement of modern SiGe processes in recent history has partially been achieved at the cost of a reduction in breakdown voltages. Because supply voltages have hardly been reduced however, circuits operating at a supply voltage above the collector-emitter breakdown voltage (BV/sub CEO/) are common practice today and collector-base avalanche currents are therefore of major concern. Transistors that need to handle a collector-emitter voltage above (BV/sub CEO/) are typically found as output transistors in output driver stages and in bias current circuits. Such circuits can be designed to tolerate collector-emitter voltages above (BV/sub CEO/) by driving the base terminal with a relatively low impedance. This paper analyzes various conventional as well as two new bias current circuits supporting operation at collector voltages above (BV/sub CEO/). In the new circuits, feedforward and feedback avalanche current compensation techniques are introduced that obtain a substantial increase in output breakdown voltage of the bias circuits and improve the accuracy of the current mirror at output voltages above (BV/sub CEO/). With the feedback technique, a measured increase in output breakdown voltage by more than 2 V is demonstrated while the accuracy of the current mirror ratio at output voltages of 2 to 3 times (BV/sub CEO/) is improved by an order of magnitude.     

Breakdown enhancement in silicon nanowire p-n junctions

We demonstrate highly reproducible silicon nanowire diodes fabricated with a fully VLSI compatible etching technology, with diameters down to 30 nm. A contact technology based on recrystallized polysilicon enables specific contact resistances as low as rho approximately 10-7 Omega cm2. Our devices show a strongly diameter-dependent breakdown voltage at reverse bias, which we explain in terms of the influence of the surrounding dielectric. We suggest that this technology is suitable for incorporating nanowire-based functionalities into future integrated circuits.     

A better insight into the performance of silicon BJTs featuringhighly nonuniform collector doping profiles

This paper investigates the effects of highly nonuniform collector doping profiles on the speed and breakdown performance of silicon bipolar transistors. Monte Carlo and drift diffusion simulation results point out that a thin highly doped layer adjacent to the base collector junction can improve the device cut off frequency without deteriorating significantly the maximum oscillation frequency and the breakdown voltage, provided the voltage drop across this layer is lower than an effective threshold of approximately 1.2 V. Guidelines are given for choosing the doping, position, and thickness of this layer