A general-purpose high-speed equalizer

The circuit presented is a high-speed self-adaptive filter achieving equalization over a wide range of signals, with a frequency of up to 40.5 MHz, as for the European D2-MAC and high-definition multiplexed analog components (HD-MAC) transmission standards. The circuit is a self-adaptive 16-tap transversal filter achieving equalization on any 8-b coded signal. It contains periodically a window of binary or duobinary data samples, such as the D, D2, and HD-MAC signals. This chip includes a delay line of 240 8-b data samples which are used for the internal gradient computations. Only linear distortions (echos) can be corrected by this chip. This 105000-transistor chip has been designed in a CMOS 1.0-μm technology and is being used in a D2-MAC reception environment     

A 54-MHz CMOS programmable video signal processor for HDTVapplications

A 54-MHz CMOS video processor with a systolic architecture suited for two-dimensional symmetric FIR (finite impulse response) filtering is reported. The circuit is a one-dimensional digital filter comprising a control part and an array of eight multiplication-accumulation cells. This processor is capable of handling 32 equivalent multiply-add operations in a sampling period as short as 18 ns. Devices can be cascaded to increase the order of the filter in both dimensions, up to 1024 stages with no truncation errors. It has been developed in a 1.2-μm CMOS technology, and it dissipates less than 500 mW at a 54-MHz clock frequency     

Outils spécialisés de synthèse VLSI pour algorithmes de traitement numérique du signal

Special-purpose silicon compilers are instrumental in making possible efficient implementations of complex digital signal processing systems on a single chip. This paper presents three such tools, each of them adapted to a specific kind of algorithm and throughput range, that generate the layout of avlsi block, based on a fixed target architecture, directly from its high-level specification. Fidys and Genrif respectively generate recursiveldi andfir vlsi digital filters, starting from behavioral frequency template specifications. The architecture is a direct one to one mapping from the filter structure. Fidys targets low-end and medium-range applications, using bit-serial architecture, whereas the bit-parallel architecture in Genrif is better adapted to high-end video applications. Cots is a more general-purpose tool that implements any C program on a customized microcoded datapath.     

A fast single-chip implementation of 8192 complex point FFT

Large-scale single-frequency networks are now being considered in Europe as very promising network topologies to achieve drastic savings in spectrum usage for digital terrestrial television transmission. Such networks are possible using the COFDM system, with large guard intervals (more than 200 μs) to absorb long echoes. In order to limit the spectral efficiency loss to about 20%, very long size fast Fourier transforms (up to 8 K complex points) have to be performed in real time for the demodulation of every COFDM symbol (every 1 ms). This paper presents the first VLSI single chip dedicated to the computation of direct or inverse fast Fourier transforms of up to 8192 complex points. Due to its pipelined architecture, it can perform an 8 K FFT every 400 μs and a 1 K FFT every 50 μs. All the storage is onchip, so that no external memories are required. A new internal result scaling technique, called convergent block floating point, has been introduced in order to minimize the required storage for a given quantization noise, The chip, 1 cm² large with 1.5 million transistors, has been designed in a 3.3 V-0.5 μm triple-level metal CMOS process and is fully functional. The 8 K complex FFT function could therefore be introduced in the coming years in digital terrestrial TV receivers at low cost