Implementation of IEEE 802.16e Standard on Xilinx ZC706: A C-RAN Prototype

Wireless Personal Communications - In this paper, we propose an architecture to implement IEEE 802.16e transmitter and receiver physical (PHY) layer on field programmable gate arrays. Several...     

Effect of Annealing Treatments on the Microstructure and Texture Development in API 5L X60 Microalloyed Pipeline Steel

Effect of annealing treatments at 600, 800, 1000 and 1200 °C on the microstructure, texture, grain boundary characteristic and recrystallization fraction of Nb-microalloyed X60 steel is evaluated by using x-ray diffraction and EBSD techniques. The results indicate that bimodal as-received microstructure is changed to a homogeneous equiaxed grain structure above annealing at 1000 °C. Macro-texture investigations depict that increasing annealing temperature results in considerable variation of texture intensity, especially at 1200 °C. Maximum intensity corresponds to {001}〈310〉, Goss, copper texture components as well as near γ-fiber at 1200 °C. Recrystallization analysis shows that volume fraction of recrystallization noticeably is increased by annealing temperature at 1200 °C. Recrystallized grains are mainly oriented along γ-fiber, especially close to {111}〈112〉 texture component. Moreover, coincidence site lattice (CSL) analysis shows that the effect of annealing temperature on the volume fraction of Σ3 boundary is negligible.     

Thermal analysis of microwave GaN‐HEMTs in conventional and flip‐chip assemblies

Temperature rising which originates from self‐heating degrades the electrical characteristics, reliability, and lifetime of high‐power GaN‐HEMTs. In this article, a systematic analytical approach for thermal evaluation of microwave GaN‐HEMTs is constructed through combining and scrutinizing some of the basic static thermal analysis methods to provide a deeper insight into the process of the channel temperature rising and self‐heating with a much lower computational burden. The proposed systematic thermal analysis has been applied to two different assembly methods: conventional mounting and flip‐chip mounting. Although the mathematical and empirical equations used are simple enough to save time, the effects of several phenomena and different conditions on the channel temperature have been taken into account. These include heat crowding phenomenon, the effect of temperature‐dependent thermal conductivity of the transistor constituent materials, transistor geometry, die‐attach material properties, and bump dimensions. To validate the accuracy of the calculations, all the analytical analyses are followed by 3D thermal simulations in ANSYS software. The simulation results confirm the accuracy of the analytical calculations.     

An enhanced quasi-monolithic integration technology for microwave and millimeter wave applications

A new technology for integration of high frequency active devices into low cost silicon substrate has been introduced. The novel fabrication process gives excellent advantages such as extremely low thermal resistance, and a much lower thermo-mechanical stress than the earlier quasimonolithic integration technology (QMIT) concept . This highly improves the packaging lifetime and electrical characteristics of the active devices. The fabrication process is simple and compatible with fabrication of high-Q passive elements. Successful integration of high-Q passive elements on low resistivity silicon substrate in this technology has been possible for the first time. In comparison to the earlier concept of QMIT, elimination of air-bridges in this technology not only reduces the parasitic elements but also enables the fabrication of the rest of the circuit after measuring the microwave characteristics of the embedded active devices. This makes very accurate microwave and millimeter-wave designs possible. Using the new fabrication process, microwave and millimeter-wave circuits (with both coplanar and microstrip lines) containing power devices have for the first time been possible. Furthermore, the enhanced QMIT can be considered as an organic deposited multi chip module (MCM-D), which is a potential candidate for integration an system on a package (SOP) at microwave and millimeterwave frequencies.     

Efficiency enhancement by employing the transistor nonlinear capacitors effects in a 6W hybrid X‐band Class‐J power amplifier

This article presents the design and fabrication of a 6 W X‐band hybrid Class‐J power amplifier (PA) based on a bare die GaN on SiC HEMT by accurate implementing the transistor nonlinear capacitor effects. The transistor input capacitor is precisely modelled and its nonlinearity effects on Class‐J performance is studied for the first time. It is shown that the harmonic generation property of the nonlinear input capacitor, especially at the second harmonic, can be of benefit to shape the transistor gate voltage as a quasi‐half wave sinusoidal waveform and consequently, it can improve the power added efficiency (PAE). A complete 3D thermal model of the power transistor is developed using ANSYS software and it is calibrated based on the thermal measured data. The PA achieves 13 dB average power gain over the frequency range of 8.8‐9.6 GHz. The drain efficiency and PAE are about 67% and 58% at 9.2 GHz, respectively.     

A voltage-dependent channel length extraction method for MOSFET’s

In this paper a new method for extraction of the channel length and channel resistance as a function of gate-voltage in MOSFET’s is introduced. The method is accurate and calculates the threshold voltages of all devices with different gate-lengths. The channel resistance is divided in two parts; the first part is a function of gate-voltage and threshold voltage difference (V_g − V_t) and the second part is only a function of gate-voltage. Further, the model determines the threshold voltage of short-channel devices independent of their parasitic resistances and implements the channel mobility as an arbitrary function of gate-voltage while the gate-voltage-dependent part of the resistance is uniquely separated from the first part of channel resistance for all devices.