Conformational Molecular Switches for Post-CMOS Nanoelectronics

Theoretical treatments forecast that bistable CMOS devices using electronic charge as a state variable will operate at their maximum thermal dissipation limit possibly as early as 2012. The problem is further compounded by increasing manufacturing challenges associated with the ever decreasing logic switch dimensions. These challenges require the development of new fabrication strategies that replace or complement current top-down lithography with bottom-up protocols using controlled self-assembly of nanomaterial building blocks. To answer some of these issues, this paper focuses on a new device paradigm consisting of an arene-metal-arene conformational switch, addressable through capacitive, inductive, or resonant-tunneling field coupling. The operating principle is based on voltage-tunable modulation in quantum electron transmission. The switch is open (off) when the metal ion is displaced to a position at a C-H bond on the arene ring due to an externally applied bias. Conversely, when the external bias is removed, the metal ion moves to an axis- symmetric position on the arene ring, and the switch is closed (on). The paper presents a summary of the architecture, operating principle, and advantages of the conformational switch, along with associated findings from proof-of-concept theoretical and experimental studies of its target specifications and performance. The paper also discusses opportunities and challenges related to the integration of conformational switches into hybrid CMOS-molecular and monolithic (all molecular) circuits.     

Interconnect limits on gigascale integration (GSI) in the 21stcentury

Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication, and thermodynamic theories, which immutably restrict interconnect performance, energy dissipation, and noise reduction. At the material level, the conductor resistivity increases substantially in sub-50-nm technology due to scattering mechanisms that are controlled by quantum mechanical phenomena and structural/morphological effects. At the device and circuit level, interconnect scaling significantly increases interconnect crosstalk and latency. Reverse scaling of global interconnects causes inductance to influence on-chip interconnect transients such that even with ideal return paths, mutual inductance increases crosstalk by up to 60% over that predicted by conventional RC models. At the system level, the number of metal levels explodes for highly connected 2-D logic megacells that double in size every two years such that by 2014 the number is significantly larger than ITRS projections. This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands. One potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance. Increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, yields an improvement in interconnect performance of up to 145% at the 50-nm node     

Low-temperature metal-organic chemical vapor deposition (LTMOCVD) of device-quality copper films for microelectronic applications

Copper films for potential use in multilevel metallization in ULSIC’s were produced by low temperature (250–350° C) metal-organic chemical vapor deposition (LTMOCVD) in atmospheres of pure H₂ or mixture Ar/H₂ from the β-diketonate precursor bis(1,1,1,5,5,5-hexafluoroacetylacetonato) copper(ll), Cu(hfa)₂. The films were analyzed by x-ray diffraction (XRD), Rutherford backscattering (RBS), Auger electron spectroscopy (AES), scanning electron microscopy (SEM), and energy-dispersive x-ray spectroscopy (EDXS). The results of these studies showed that the films were uniform, continuous, adherent and highly pure—oxygen and carbon contents were below the detection limits of AES. Four point resistivity measurements showed that the copper films had very low resistivity, as low as 1.9 μΩcm for the films deposited in pure hydrogen atmosphere. Our preliminary results seem to indicate that LTMOCVD is a very attractive technique for copper multilevel metallizations.     

ZERO THICKNESS DIFFUSION BARRIERS AND METALLIZATION LINERS FOR NANOSCALE DEVICE APPLICATIONS

A robust diffusion barrier and metallization liner technology are critical for the realization of a functional and reliable interconnect structure. While copper barrier materials and processes have evolved significantly since the onset of copper-based metallization, the extendibility of existing barrier/liner solutions for use in emerging nanoscale interconnect structures faces a number of significant challenges related to the continued scaling of IC feature sizes. A key element in addressing these challenges includes developing an understanding of the mechanisms that lead to barrier failure and subsequent interconnect reliability deficiencies, and identifying how such mechanisms differ in the nanoscale regime from their counterparts at the microscale regime. In this respect, it is important that these distinctions serve as baseline in establishing the factors that determine the relevance and applicability of potential barrier solutions. Furthermore, it is critical to understand how these factors have evolved as barrier layers scaled to thicknesses of a few atoms. Accordingly, the current report outlines short- and long-term trends for these technologies.