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Socrates D. Vamvakos Claude R. Gauthier Chethan Rao Alvin Wang Karthisha Ramoshan Canagasaby Khaldoon Abugharbieh Prashant Choudhary Sanjay Dabral Shaishav Desai Mahmudul Hassan K. C. Hsieh Bendik Kleveland Gurupada Mandal Richard Rouse Ritesh Saraf Jason Yeung Ying Cao 《Analog Integrated Circuits and Signal Processing》2014,78(2):259-273
This paper presents the design and Silicon verification of a 2.488–11.2 Gbps multi-standard SerDes transceiver in a 40 nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process. A system modeling approach is described, which is used for optimizing the architectural trade-offs. The transceiver makes use of a low-jitter LC phase locked loop to enable high-reliability system design. The design has 420 fs RJrms and consumes 30.1 mW/Gbps at 11.2 Gbps. 相似文献
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