Built-in testable error detection and correction

A method for design of built-in testable (BIT) error detection and correction (EDAC) circuits is presented that uses up to 65% less test hardware than customary BIT implementations. A 1-μm CMOS, 16-bit EDAC designed and fabricated with this technique exhibits >99% fault coverage in 10 μs at 25 MHz. Built-in test impacts the speed performance by only one gate delay regardless of the size of the EDAC. Various faults are injected into the chip to verify the effectiveness of built-in test     

Built-in test of CMOS state machines with realistic faults: asystem perspective

The design of built-in test systems for large arrays is approached from the viewpoint of detecting real faults in the mask layers of a typical CMOS process. The resulting testable design and built-in test system provides a practical compromise between the costly hardware augmentation plaguing existing techniques and circuit independence of the test procedure. Built-in testability is achieved independently of feedback. Therefore, combinational and sequential circuits can be tested in parallel with exactly the same hardware and method. The test-specific hardware overhead decreases rapidly with increasing circuit size and falls below 10% for large arrays with more than 100 product terms. No additional gate delays are introduced into the critical path by the test circuitry. The normal circuit performance is, therefore, left intact with the exception of a minimal degradation associated with adding tristate capability to the input buffers