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In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the reseeding is performed on-the-fly by inverting the logic value of some of the bits of the next state of the Test Pattern Generator (TPG). The proposed reseeding technique is generic and can be applied to TPGs based on both Linear Feedback Shift Registers (LFSRs) and accumulators. An efficient algorithm for selecting reseeding points is also presented, which targets complete fault coverage and allows to well exploiting the trade-off between hardware overhead and test length. Using experimental results we show that the proposed method compares favorably to the other already known techniques with respect to test length and the hardware implementation cost.  相似文献   
2.
Various compression methods have been proposed for tackling the problem of increasing test-data volume of contemporary, core-based systems. Despite their effectiveness, most of the approaches that are based on classical codes (e.g., run-lengths, Huffman) cannot exploit the test-application-time advantage of multiple-scan-chain cores, since they are not able to perform parallel decompression of the encoded data. In this paper, we take advantage of the inherent parallelism of Huffman decoding and we present a generalized multilevel Huffman-based compression approach that is suitable for cores with multiple scan chains. The size of the encoded data blocks is independent of the slice size (i.e., the number of scan chains), and thus it can be adjusted so as to maximize the compression ratio. At the same time, the parallel data-block decoding ensures the exploitation of most of the scan chains' parallelism. The proposed decompression architecture can be easily modified to suit any Huffman-based compression scheme.  相似文献   
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