New directions in semicustom arrays

The CMOS Gate Forest is such a semicustom array which offers an integration level comparable to that of a full-custom VLSI environment. A hierarchical design approach has become essential in order to be able to handle the complexity of such an implementation environment. Although the Gate Forest is representative of second-generation gate arrays, it also incorporates a number of unique features. The Gate Forest is used to describe the major features of a current semicustom design environment. Partitioning, floorplanning, and mapping operation characteristics are described. Current status of the different parts of the Gate Forest design environment are described     

Mixed static and domino logic on the CMOS gate forest

In a semicustom design environment with unified transistor geometries, logic circuit optimization is achieved using an efficient physical circuit implementation. In particular, the semicustom realization of domino logic is demonstrated with a standard-cell and a multiplier design which are used to support the implementation of such a dynamic logic design style on a gate forest, which has a higher n count than p count. The mixture of complementary and dynamic logic allows the designer to improve the critical-path delay and to reduce the size of the layout. The domino standard-cell architecture supports multiple-output configurations and additional internal precharge. The operation time for a mixed static/dynamic multiplier is approximately 30% higher than that of the static version based on a carry select adder. This difference mainly affects the critical delay of the sign-extension path of the parallel adder array     

High-speed CMOS adder and multiplier modules for digital signalprocessing in a semicustom environment

For the realization of digital filters in a semicustom environment, high-performance adder and multiplier modules have been developed. These modules define the performance limits for digital finite impulse response (FIR) filters. The Gate Forest semicustom environment is a sea-of-gates-type transistor array. It supports the implementation of dynamic (domino) CMOS logic circuits. The circuit-design technique is applicable to compact high-speed designs. The realized dynamic adder architecture consists of a 2-b group adder and a Manchester carry chain (MCC). For an N-b addition this results in a N/2-b carry lookahead path. This dynamic adder scheme can be expanded into 4-b group adder modules. The multiplier module is a combination of a modified Booth-coded static adder array with a final dynamic MCC adder. The multiplier is clocked with a single (symmetric) clock signal. The clock signal is divided into a precharge pulse, in which the static part of the multiplier added array is evaluated, and an evaluation phase for the generation of the multiplication result (least significant bits). A 16-b×16-b multiplier based on this architecture runs with a 40-MHz system clock. The first chips have been processed in a 2-μm CMOS double-metal technology     

The CMOS gate forest: an efficient and flexible high-performanceASIC design environment

The basic concepts of the second-generation gate arrays are described. The most important architectures that were used to implement the different concepts are discussed. An overview of the current status of a number of typical sea-of-gates masters is given. A number of quality marks have been defined along which the different architectures can be evaluated. These quality marks range from microarchitecture aspects such as isolation techniques and connectability of the core cells, to macro aspects such as distribution functions. Using these quality marks for reference, the Gate Forest is discussed. The Gate Forest is seen as a major extension of the sea-of-gates principle. It differs from the extant sea-of-gates concept in several important aspects. It is based on a hierarchical concept, both in architecture and design. It combines flexibility and efficiency in one environment by providing transistor-level optimization together with cell library support for different logic design styles. It furthermore supports the efficient implementation of different types of memory in any desired location. The current status of the second generation of the Gate Forest is also briefly described