Photonic page buffer based on GaAs multiple-quantum-well modulators bonded directly over active silicon complementary-metal-oxide-semiconductor (CMOS) circuits

We present a 2-kbit, 50-Mpage/s, photonic first-in, first-out page buffer based on gallium arsenide/aluminium-gallium arsenide multiple-quantum-well diodes that are flip-chip bonded to submicrometer silicon complementary-metal-oxide-semiconductor circuits. This photonic chip provides nonvolatile storage (buffering), asynchronous-to-synchronous conversion, bandwidth smoothing, tolerance to jitter or skew, spatial format conversion, wavelength conversion, and independent flow control for the input and the output channels. It serves as an interface chip for parallel-accessed optical bit-plane data. It represents the first smart-pixel array that accomplishes the vertical integration of multiple-quantum-well modulators and detectors directly over active silicon VLSI circuits and provides over 340 transistors per optical input-output. Results from high-speed single-channel testing and real-time array operation of the photonic page buffer are reported.     

Dual-function detector-modulator smart-pixel module

We describe a smart-pixel circuit that permits the use of a GaAs/AlGaAs multiple quantum well diode to be used both as a detector for data input and a modulator for data output. The module provides the ability to double the number of inputs or outputs to the array and is well suited to cascaded optoelectronic system architectures that require bidirectional communition.     

The AMOEBA switch: an optoelectronic switch for multiprocessornetworking using dense-WDM

We present a single-chip asynchronous multiprocessor optoelectronic bit-sliced arrayed (AMOEBA) crossbar switch. The AMOEBA switch addresses the challenge to produce a large-scale, nonblocking packet switch through dense integration of photonic devices directly onto silicon VLSI circuits. Optoelectronic-VLSI technology is used to integrate the switch fabric, routing controller, packet buffers, line interface circuits, and optoelectronic conversion devices on a single chip. We show how free-space optical interconnects and wavelength-and-space-division-multiplex networking on single-mode fibers can provide switched interconnection between multiple nodes in a distributed computing environment. An optomechanical transceiver package accomplishes the free-space-to-fiber interfacing. We report the implementation and testing of the key components of a 16-channel AMOEBA prototype switch with a potential capacity of 12.8 Gb/s (or 800 Mb/s/channel), and capable of switching 16 million packets per second     

Ring oscillators with optical and electrical readout based onhybrid GaAs MQW modulators bonded to 0.8 μm silicon VLSIcircuits

Loaded and unloaded ring-oscillator circuits with an electrical and surface-normal 850 nm optical readout are fabricated using a hybrid 0.8 μm silicon-CMOS/GaAs-AlGaAs MQW process. Measurements of the oscillation frequency of these circuits show total capacitance associated with the flip-chip-bonded optical MQW modulators as low as 52 fF     

Flip Chip Bonding of 68 $times$ 68 MWIR LED Arrays

The flip chip bonding process is optimized by varying the bonding pressure, temperature, and time. The 68times68 mid wave infrared (MWIR) LED array was hybridized onto Si-CMOS driver array with same number of pixels. Each pixel has two indium bumps, one for cathode and another for anode. Both LED array and CMOS drivers have 15-mum-square Indium bump contact pads. We used Karl Suss FC150 flip chip machine for bonding of CMOS driver array onto LED array. From the LED current-voltage characteristics, it is concluded that the optimized flip chip bonding process results in uniform contact and very low contact resistance. Both electrical and optical characteristics of LED array after flip chip bonding are presented.     

Kernel-based sparse representation for gesture recognition

In this paper, we propose a novel sparse representation based framework for classifying complicated human gestures captured as multi-variate time series (MTS). The novel feature extraction strategy, CovSVDK, can overcome the problem of inconsistent lengths among MTS data and is robust to the large variability within human gestures. Compared with PCA and LDA, the CovSVDK features are more effective in preserving discriminative information and are more efficient to compute over large-scale MTS datasets. In addition, we propose a new approach to kernelize sparse representation. Through kernelization, realized dictionary atoms are more separable for sparse coding algorithms and nonlinear relationships among data are conveniently transformed into linear relationships in the kernel space, which leads to more effective classification. Finally, the superiority of the proposed framework is demonstrated through extensive experiments.     

Performance comparison between optoelectronic and VLSI multistageinterconnection networks

The performance characteristics of optoelectronic and VLSI multistage interconnection networks are compared. The bases of the comparison include speed, bandwidth, power consumption, and footprint area. The communication network used in the comparison is a synchronous packet-switched multistage interconnection network built from 2×2 bit-serial switching elements. CMOS technology was used in the VLSI implementation, and it is assumed that the entire network resides on a single chip. Regular free-space optical interconnects are used in the optoelectronic implementation. The results show that for large networks optoelectronics offers higher speed and lower area than VLSI. Based on the assumed technology parameters, optoelectronics outperforms VLSI in bandwidth for network sizes above 256     

A 2-Gb/s 0.5-/spl mu/m CMOS parallel optical transceiver with fast power-on capability

This paper describes an optical transceiver designed for power-efficient connections within high-speed digital systems, specifically for board- and backplane-level interconnections. A 2-Gb/s, four-channel, dc-coupled differential optical transceiver was fabricated in a 0.5-/spl mu/m complementary metal-oxide-semiconductor (CMOS) silicon-on-sapphire (SoS) process and incorporates fast individual-channel power-down and power-on functions. A dynamic sleep transistor technique is used to turn off transceiver circuits and optical devices during power-down. Differential signaling (using two optical channels per signal) enables self-thresholding and allows the transceiver to quickly return from power-down to normal operation. A free-space optical link system was built to evaluate transceiver performance. Experimental results show power-down and power-on transition times to be within a few nanoseconds. Crosstalk measurements show that these transitions do not significantly impact signal integrity of adjacent active channels.     

Automated design of integrated circuits with area-distributed input-output pads

We present a method for automating the creation of complementary-metal-oxide-semiconductor (CMOS) integrated circuits that successfully utilizes a large number of area-distributed pads for input-output communication. This method uses Duet Technologies' epoch computer-aided-design tool for automated placement and routing of CMOS circuitry, given a schematic netlist as an input. The novelty of this approach is that it uses Duet Technologies' eggo program to place and route area-pad signals. To verify this methodology, it is applied to the design of a digital signal-processing circuit, with 200 optical area-pad input-outputs and 44 perimeter-pad input-outputs, that is being fabricated with Bell Labs 1997 CMOS-multiple-quantum-well foundry. The layout results are as good as or better than the results obtained by manual layout.