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I. V. Antonova V. P. Popov D. V. Kilanov E. P. Neustroev A. Misuk 《Semiconductors》1999,33(10):1049-1053
This paper discusses the generation of thermal donor centers in silicon by oxygen ion implantation in the temperature range
350 to 550 °C. These donors are distributed almost uniformly over the entire thickness of the silicon crystals and well outside
the region of direct penetration of the ions. It is established that implantation of Czochralski-grown silicon with oxygen
ions followed by annealing accelerates the introduction of these donors into the silicon, and that application of hydrostatic
pressure further accelerates the process of donor-center formation. The data indicate that this accelerated introduction of
donors is associated with diffusion of radiation-induced defects from the implanted layer into the crystal bulk, and that
the diffusion coefficients of these defects are 1×10−7 cm2/s or larger.
Fiz. Tekh. Poluprovodn. 33, 1153–1157 (October 1999) 相似文献
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D. V. Kilanov V. P. Popov L. N. Safronov A. I. Nikiforov R. Sholz 《Semiconductors》2003,37(6):620-624
Formation of interior hydrogen-passivated surfaces in hydrogen-implanted single-crystal Si containing a buried layer heavily doped with boron is investigated. With the use of the infrared absorption spectroscopy, it is shown that, upon annealing, the composition of hydrogen-containing defects in Si samples containing a buried heavily doped layer is the same as in Si samples that do not have such a layer. However, the presence of a heavily doped layer enhances the blistering and exfoliation of a thin silicon film from the Si sample, and the activation energies of the relevant processes change. Thus, the process of development of cavities in such layers changes upon thermal annealing. The depth at which hydrogen-passivated surfaces are formed corresponds to the projected range of H ions in Si, which also corresponds to the depth at which the B-doped layer is located. When a thin exfoliated film is transferred onto an insulator to form a silicon-on-insulator structure, the surface roughness of the film decreases by a factor of 2–5. 相似文献
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Popov V. P. Antonova I. V. Frantsuzov A. A. Safronov L. N. Popov A. I. Naumova O. V. Antonenko A. Kh. Kilanov D. V. Mironova I. V. 《Russian Microelectronics》2002,31(4):232-237
DeleCut, a new technology for producing SOI structures, is presented [1]. It is an improvement on the SmartCut® process. DeleCut allows one to reduce annealing temperature and offers a lower concentration of radiation defects, a thinner transferred silicon layer, and a thinner transition layer between the silicon and the insulator (oxide). This process technology makes it possible to obtain silicon and insulator layers whose thicknesses are uniform within a few nanometers. A batch of SOI wafers of diameter 100–150 mm is fabricated with a pilot production line, the silicon films being free from dislocations. On the basis of the SOI structures, several types of submicrometer test CMOS circuits are successfully produced. 相似文献
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V. P. Popov A. I. Antonova A. A. Frantsuzov L. N. Safronov G. N. Feofanov O. V. Naumova D. V. Kilanov 《Semiconductors》2001,35(9):1030-1037
The physical grounds for making SOI structures by the DeleCut (ion irradiated deleted oxide cut) method are considered. This
method is a modification of the commonly known Smart Cut? technique and aims at eliminating the disadvantages of the basic
method [1]. The proposed method makes it possible to considerably lower the annealing temperature and the content of radiation
defects in SOI structures. It allows the thickness of a split-off Si layer and a transition layer between the SOI layer and
a buried oxide to be reduced. The method also reduces the nonuniformity in the thickness of the SOI layer and the insulator
to several nanometers. By using DeleCut, new SOI structures were formed on wafers with diameters as large as 150 mm; the structures
included dislocation-free SOI layers of 0.003–1.7 μm in thickness and a buried thermal SiO2 oxide (0.05–0.5 μm). These structures have good electrical characteristics, which is supported by fabricating the submicrometer
(0.2–0.5 μm) SOI-based CMOS transistors and test integrated circuits.
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Translated from Fizika i Tekhnika Poluprovodnikov, Vol. 35, No. 9, 2001, pp. 1075–1083.
Original Russian Text Copyright ? 2001 by Popov, Antonova, Frantsuzov, Safronov, Feofanov, Naumova, Kilanov. 相似文献
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