Acquisition-time estimation for over 10 Gbit/s clock and data recovery ICs

A method to estimate the acquisition time for the clock and data recovery (CDR) IC using the linear phase-locked loop (PLL) technique is proposed. Estimations using the method follow the measured acquisition time for the PLL with any loop parameters, which makes it possible to design the CDR IC for various targets.     

PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits

A design technique for an over-10-Gb/s clock and data recovery (CDR) IC provides good jitter tolerance and low jitter. To design the CDR using a PLL that includes a decision circuit with a certain phase margin affecting the pull-in performance, we derived a simple expression for the pull-in range of the PLL, which we call the "limited pull-in range," and used it for the pull-in performance evaluation. The method allows us to quickly and easily compare the pull-in performance of a conventional PLL with a full-rate clock and a PLL with a half-rate clock, and we verified that the half-rate PLL is advantageous because of its wider frequency range. For verification of the method, we fabricated a half-rate CDR with a 1:16 DEMUX IC using commercially available Si bipolar technology with f/sub T/=43 GHz. The half-rate clock technique with a linear phase detector, which is adopted to avoid using the binary phase detector often used for half-rate CDR ICs, achieves good jitter characteristics. The CDR IC operates reliably up to over 15 Gb/s and achieves jitter tolerance with wide margins that surpasses the ITU-T specifications. Furthermore, the measured jitter generation is less than 0.4 ps rms, which is much lower than the ITU-T specification. In addition, the CDR IC can extract a precise clock signal under harsh conditions, such as when the bit error rate of input data is around 2/spl times/10/sup -2/ due to a low-power optical input of -24 dBm.     

Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/sone-chip optical receiver IC with 1: 8 DEMUX

A loop parameter optimization method for a phase-locked loop (PLL) used in wide area networks (WANs) is proposed as a technique for achieving good jitter characteristics. It is shown that the jitter characteristics of the PLL, especially jitter transfer and jitter generation, depend strongly on the key parameter ζω_n (ζ is a damping factor and ω_n is the natural angular frequency of the PLL), and that the optimization focusing on the ω_n dependence of the jitter characteristics make it possible to comprehensively determine loop parameters and loop filter constants for a PLL that will fully comply with ITU-T jitter specifications. Using the optimization method with the low-jitter circuit design technique, a low-jitter and low-power 2.5-Gb/s optical receiver IC integrated with a limiting amplifier, clock and data recovery (CDR), and demultiplexer (DEMUX) is fabricated using 0.5-μm Si bipolar technology (f_T = 40 GHz). The jitter characteristics of the IC meet all three types of jitter specifications given in ITU-T recommendation G.783. In particular, the measured jitter generation is 3.2 ps rms, which is lower than that of an IC integrated with only a CDR in our previous work. In addition, the pull-in range of the PLL is 50 MHz and the power consumption of the IC is only 0.68 W (limiting amplifier: 0.2 W, CDR (PLL): 0.3 W, DEMUX: 0.18 W) at a supply voltage of -3.3 V and only 0.35 W at a supply voltage of -2.5 V (without output buffers)     

A high-speed, low-power bipolar digital circuit for Gb/s LSI's:current mirror control logic

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF)     

Low-jitter design method based on Wn-domain jitter analysis for 10 Gbit/s clock and data recovery ICs

A low-jitter design method based on vn-domain jitter analysis for the clock and data recovery (CDR) ICs using the linear phase-locked loop (PLL) is proposed. Using this method, the loop parameters of the PLL can be optimised, which makes it possible to design the CDR IC for various targets.     

Reliability of molecular weight determination methods for oligomers investigated using certified polystyrene reference materials

Using polystyrene certified reference materials (CRMs) whose molecular weights range from 500 to 2400, we investigated the reliability of molecular weight determination by size-exclusion chromatography (SEC), SEC coupled with multi-angle light scattering detection (SEC-MALS), conventional static light scattering (SLS), matrix-assisted laser desorption/inonization time-of-flight mass spectrometry (MALDI-TOFMS), and ¹H NMR. Average molecular weights determined by these methods were compared with the certified values which were determined by supercritical fluids chromatography with relative standard uncertainty less than 1%. The comparison showed that recent SEC with calibration constructed by uniform polystyrenes can provide just the same average molecular weights as certified ones within the standard uncertainty. ¹H NMR was also found to be a powerful technique to determine number-average molecular weight accurately. Average molecular weights measured by SEC-MALS and SLS nearly agreed with certified values except for lower molecular weights. Although MALDI-TOFMS provided average molecular weights in agreement with certified values, the polydispersity given by MALDI-TOFMS were found to be very small for all the polystyrenes.     

Fast-acquisition PLL using fully digital natural-frequency-switching technique

A new phase-backed loop (PLL) with a simple architecture that overcomes the trade-off problem between acquisition time and phase noise was fabricated in a 0.2 mum CMOS process. One-fifth of the acquisition time of the integer-JV is achieved by switching only the division ratio with the optimised damping factor to control the natural frequency.     

A 2.5-Gb/s clock and data recovery IC with tunable jittercharacteristics for use in LANs and WANs

A 2.5-Gb/s monolithic clock and data recovery (CDR) IC using the phase-locked loop (PLL) technique is fabricated using Si bipolar technology. The output jitter characteristics of the CDR can be controlled by designing the loop-gain design and by using the switched-filter PLL technique. The CDR IC can be used in local-area networks (LANs) and in long-haul backbone networks or wide-area networks (WANs). Its power consumption is only 0.4 W. For LANs, the jitter generation of the CDR when the loop gain is optimized is 1.2 ps (0.003 UI). The jitter characteristics of the CDR optimized for WANs meet all three types of STM-I6 jitter specifications given in ITU-T Recommendation G.958. This is the first report on a CDR that can be used for both LAN's and WAN's. This paper also describes the design method of the jitter characteristics of the CDR for LANs and WANs     

Supersonic two-phase flow of CO2 through converging–diverging nozzles for the ejector refrigeration cycle

CO₂ is environmentally friendly, safe and more suitable to ejector refrigeration cycle than to vapor compression cycle. Supersonic two-phase flow of CO₂ in the diverging sections of rectangular converging–diverging nozzles was investigated. The divergence angles with significant variation of decompression were 0.076°, 0.153°, 0.306° and 0.612°. This paper presents experimental decompression phenomena which can be used in designing nozzles and an assessment of Isentropic Homogeneous Equilibrium (IHE). Inlet conditions around 6–9 MPa, 20–37 °C were used to resemble ejector nozzles of coolers and heat pumps. For inlet temperature around 37 °C, throat decompression boiling from the saturated liquid line, supersonic decompression and IHE solution were obtained for the two large divergence angles. For divergence angles larger than 0.306°, decompression curves for inlet temperature above 35 °C approached IHE curves. For divergence angles smaller than 0.306° or for nozzles with inlet temperature below 35 °C, IHE had no solution.