New results using membrane-supported circuits: a Ka-band poweramplifier and survivability testing

This paper describes recent results which pertain to the integration and reliability testing of micromachined, membrane-supported transmission line circuits. These circuits employ a 1.4-μm-thick dielectric membrane to support thin-film conducting lines above an air substrate. With regard to integration, the development of a Ka-band solid state power amplifier (SSPA) is presented. The design includes a membrane-supported Wilkinson power divider/combiner with 0.2 dB loss, along with a commercially available monolithic microwave/millimeter wave integrated circuit (MMIC) amplifier stage. Also reported are tests which investigated the survivability of membrane lines under space qualification conditions. No failures occurred as a result of thermal cycling and vibration testing at levels which reached 39.6 grms     

Ti-Si-N diffusion barriers between silicon and copper

Thin films of Ti-Si-N, reactively spattered from a Ti₅Si₃ target, are assessed as diffusion barriers between silicon substrates and copper overlayers. By tests on shallow-junction diodes, a 100 nm Ti₃₄Si₂₃N₄₃ barrier is able to prevent copper from reaching the silicon substrate during a 850°C/30 min anneal in vacuum. A 10 nm film prevents diffusion up to 650°C/30 min. By high-resolution transmission electron microscopy, Ti₃₄Si₂₃N₄₃ predominantly consists of nanophase TiN grains roughly 2 nm in size     

Sputtered Ta-Si-N diffusion barriers in Cu metallizations for Si

Electrical measurements on shallow Si n⁺-p junction diodes with a 30-nm TiSi₂ contacting layer demonstrate that an 80-nm-thick amorphous Ta₃₆Si₁₄N₅₀ film prepared by reactive RF sputtering of a Ta₅Si₃ target in an Ar N₂ plasma very effectively prevents the interaction between the Si substrate with the TiSi₂ contacting layer and a 500-nm Cu overlayer. The Ta₃₆Si₁₄N₅₀ diffusion barrier maintains the integrity of the I-V characteristics up to 900 C for 30-min annealing in vacuum. It is concluded that the amorphous Ta ₃₆Si₁₄N₅₀ alloy is not only a material with a very low reactivity for copper, titanium, and silicon, but must have a small diffusivity for copper as well     

Reaction of aluminum-on-titanium bilayer with GaN: Influence of the Al:Ti atomic ratio

Backscattering spectrometry, x-ray diffractometry, and scanning electron microscopy have been used to study metallurgically the evolution of 〈GaN〉/Ti(40 nm)/Al(180 nm) and 〈GaN〉/Ti(80 nm)/Al(150 nm) metal contacts before and after annealing for 30 min in vacuum between 450 and 800°C. A slight reaction of the titanium with the aluminum is first observable after annealing at 450°C. After 550°C titanium completely converts to Al₃Ti. Major differences in the evolution of the samples are observed after annealing at 550 and 700°C depending on the atomic ratio between aluminum and titanium. With excess aluminum remaining after the Al₃Ti formation, hillocks from at 550°C and the excess Al melts at 700°C, leading to a very strong roughening of the reacted film. Titanium nitride also appears after annealing at 700°C. The roughening of the surface can be avoided by keeping the atomic ratio of aluminum to titanium below 3. In that case, the excess titanium reacts with the Al₃Ti and the second phase AlTi appears. No titanium nitride is observed in the latter case, and aluminum nitride neither, in all cases. These results still need explaining.     

Microstructure of reactively sputtered oxide diffusion barriers

Molybdenum oxide (Mo_1-x O _x ) and ruthenium oxide (RuO₂) films were prepared by rf reactive sputtering of Mo or Ru targets in an O₂/Ar plasma. Both films exhibit metallic conductivities. The influence of the deposition parameters on the phase that forms and on the microstructure of Mo_1-x O _x and RuO₂ films is reported. A phase transformation is observed in Mo_1-x O _x films subjected to heat treatment. The diffusion barrier performance of Mo_1-x O _x and RuO₂ layers interposed between Al and Si is compared.     

Tools for multiple-CPU environments

A brief overview precedes ten separate tool reviews. Five of the tools address the problems of performance analysis, testing, and debugging in a multiple-CPU environment. The first set of tools-Graspin PPSE, and Integral-supports this activity by providing specification or design languages for concurrent applications. The next pair of tools-Pie and Total-supports the development of multiple-CPU software by representing the software's behavior in a parallel or concurrent environment. The next set of five tools is aimed at the problem of serial-to-parallel conversions. The first three tools-E/SP, Mimdizer, and PRETS-recapture the design of the original source code and display it in a graphical form for analysis. The remaining tools-Pat and Aspar-support direct source-to-source transformations. These ten tools are representative of current approaches being taken to address the problem of multiple-CPU computing     

Silicon Schottky barriers and p-n junctions with highly stablealuminum contact metallization

Reactively sputtered amorphous Ta₃₆Si₁₄N₅₀ thin films are investigated as diffusion barriers to improve the thermal stability of contacts to electronic devices, specifically between Al overlayers and Si substrates. Electrical measurements on Schottky diodes and on shallow n ⁺-p junction diodes are used to evaluate the thermal stability of the (Si)/W₄₈Si₂₀N₃₂/Ta₃₆Si ₁₄N₅₀/Al metallization. The W₄₈Si₂₀N₃₂ contacting layer is added to raise the Schottky barrier height on n-type Si. It is shown that a 100-nm-thick Ta₃₆Si₁₄N₅₀ layer effectively prevents the intermixing between Al and Si. With this barrier layer, both shallow junctions and Schottky diodes are electrically stable up to 700°C for 20 min (above the Al melting point of 660°C ), which makes this material the best thin-film diffusion barrier on record     

Finite-element analysis on a PC

The authors describe how they achieved mainframe performance by coding the Cosmos/M finite-element analysis system, a commercial product, for a PC enhanced with a parallel-processing board. The discussion covers design goals, algorithm design, implementation and debugging, performance optimization, and scalability. They focus on financial, algorithmic, and numerical issues, with almost no reference to the numerical principles involved in solving stress-analysis equations     

Investigation of the four-gate action in G/sup 4/-FETs

The four-gate silicon-on-insulator transistor (G/sup 4/-FET) combines MOS and JFET actions in a single transistor to control the drain current. The various operation modes of the G/sup 4/-FET are analyzed, based on the measured current-voltage, transconductance and threshold characteristics. The main parameters (threshold voltage, swing, mobility) are extracted and shown to be optimized for particular combinations of gate biasing. Numerical simulations are used to clarify the role of volume or interface conduction mechanisms. Besides excellent performance (such as subthreshold swing and transconductance) and unchallenged flexibility, the new device has the unique feature to allow independent switching by its four separate gates, which inspires many innovative applications.     

Design for ASIC reliability for low-temperature applications

A design for reliability methodology has been developed for electronics for low-temperature applications. A hot carrier aging (HCA) lifetime projection model is proposed to take into account the HCA impact on technology, analysis of parametric degradation versus critical circuit path degradation, transistor bias profile, transistor substrate current profile, and operating temperature profile. The most applicable transistor size can be determined in order to meet the reliability requirements of the electronics operating under low temperatures. This methodology and approach can also be applied to other transistor-level failure and/or degradation mechanisms for applications with varying temperature ranges.