排序方式: 共有13条查询结果,搜索用时 31 毫秒
1.
Arjavalingam G. Pastol Y. Halbout J.-M. Kopcsay G.V. 《Microwave Theory and Techniques》1990,38(5):615-621
A broadband microwave measurement technique based on picosecond transient radiation from optoelectronically pulsed antennas is described. It is performed with exponentially tapered coplanar stripline antennas which are integrated with the photoconductive devices used for ultrafast pulse generation and sampling. The signal analysis required for deriving the desired physical properties from the measured time-domain waveforms is discussed. This is a coherent technique that independently determines both the real and the imaginary parts of the dielectric constants of materials, from 10 to 130 GHz, in a single experiment. Some representative results are presented 相似文献
2.
Deutsch A. Kopcsay G.V. Coteus P.W. Surovic C.W. Dahlen P.E. Heckmann D.L. Dah-Weih Duan 《Electromagnetic Compatibility, IEEE Transactions on》2001,43(4):446-465
This paper compares the major classes of chip-to-chip and on-chips interconnections used in high-performance computers and communication systems and reviews their electrical characteristics. Measurement results of dielectric loss are shown and the attenuation is compared for printed-circuit-board, glass-ceramic, thin-film, and on-chip wiring. Simulation results are shown with representative driver and receiver circuits, guidelines are given for when losses are significant, and predictions are made for the sustainable bandwidths on useful wiring lengths 相似文献
3.
Kopcsay G.V. Krauter B. Widiger D. Deutsch A. Rubin B.J. Smith H.H. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2002,10(6):695-711
Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix and its inverse, 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods . Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach. It then extends the extraction algorithm to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis. 相似文献
4.
Deutsch A. Smith H.H. Rubin B.J. Krauter B.L. Kopcsay G.V. 《Advanced Packaging, IEEE Transactions on》2006,29(1):11-20
A new technique is described for reducing computational complexity and improving accuracy of combined power distribution and interconnect noise prediction for wide, on-chip data-buses. The methodology uses lossy transmission-line power-blocks with frequency-dependent properties needed for the multigigahertz clock frequencies. The interaction between delta-I noise, common-mode noise, and crosstalk and their effect on timing is illustrated with simulations using representative driver and receiver circuits and on-chip interconnections. 相似文献
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6.
Ranieri VA. Deutsch A. Kopcsay G.V. Arjavalingam G. 《IEEE transactions on instrumentation and measurement》1990,39(3):504-507
An electrical probe based on specially designed coaxial tips is shown to have 24-GHz bandwidth. It can be used to test high-speed signal propagation on planar or nonplanar chip or package interconnection structures with signal/ground pads as small as 50 μm. The detailed fabrication procedure, characterization, and use of the probe are presented. A variation of the design has 500-Ω input impedance and a bandwidth of 19 GHz 相似文献
7.
Characterization and performance evaluation of differentialshielded cables for multi-Gb/s data-rates
Deutsch A. Kopcsay G.V. Surovic C.W. Coteus P.W. Lanzetta A.P. Takken T. Bond P.W. 《Advanced Packaging, IEEE Transactions on》2002,25(1):102-117
This paper compares several differential cable characteristics that were evaluated for multi-Gb/s data-rates for both data and clock paths for 1-10 m lengths. Time-domain measurements are shown for the unassembled and connectorized cables and for representative card-plus-cable signal paths and the performance limiting factors are highlighted. Techniques are shown for developing coupled-line models for odd and even excitations for all the components in a full chip-to-chip path in order to make realistic data-rate predictions 相似文献
8.
Deutsch A. Winkel T.-M. Kopcsay G.V. Surovic C.W. Rubin B.J. Katopis G.A. Chamberlin B.J. Krabbenhoft R.S. 《Advanced Packaging, IEEE Transactions on》2005,28(1):4-12
In this paper, the self-consistent, frequency-dependent dielectric constant epsivr(f) and dielectric loss tandelta(f) of several materials are determined over the range 2 to 30 GHz using a short-pulse propagation technique and an iterative extraction based on a rational function expansion. The simple measurement technique is performed in the time domain on representative printed circuit board wiring. Broadband, fully causal transmission-line models based on these results are generated up to 50 GHz for card wiring using low loss materials including BT, Nelco N4000-13, and Nelco N4000-13SI. Simulation and modeling results highlight the need for the accurate frequency-dependent dielectric loss extraction. Signal propagation based on these results shows very good agreement with measured step and pulse time-domain excitations and provides validation of the measurement and model generation technique 相似文献
9.
On-chip wiring design challenges for gigahertz operation 总被引:2,自引:0,他引:2
Deutsch A. Coteus P.W. Kopcsay G.V. Smith H.H. Surovic C.W. Krauter B.L. Edelstein D.C. Restle P.L. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》2001,89(4):529-555
This paper reviews the status of present day on-chip wiring design methodologies and understanding. A brief explanation is given of the fundamental transmission-line properties that should be considered for accurate prediction of crosstalk, common-mode noise and clock skew. The deficiencies of RC-circuit representation are highlighted and design guidelines are given for using modeling and simulation techniques that have been previously used for package interconnections. Such techniques are believed to teach designers how to make better use of available technologies and help them architect systems that operate with many-GHz clock rates 相似文献
10.
Deutsch A. Smith H.H. Surovic C.W. Kopcsay G.V. Webber D.A. Coteus P.W. Katopis G.A. Becker W.D. Dansky A.H. Sai-Halasz G.A. Restle P.J. 《Advanced Packaging, IEEE Transactions on》1999,22(3):292-308
An extensive study of crosstalk simulation issues for on-chip interconnections was performed for representative six-layer Al(Cu) structures. Guidelines are given for the range of conditions when R(f)L(f)C versus RLC versus RC circuit representations are valid. Examples are also given of realistic short and long coupled-section interactions and the effect of in-plane neighboring connections is discussed. A frequency-dependent crosstalk simulation technique is shown. All simulation results are verified through measurement of a comprehensive set of experiments built with a large range of line widths and spaces on various layers with both in-plane and vertical coupling. Signal propagation and crosstalk are analyzed over the temperature range -160°C to +100°C and interconnect bandwidth limitations predictions are given 相似文献