A Sub-Picosecond Resolution 0.5–1.5 GHz Digital-to-Phase Converter

A digital-to-phase converter (DPC) is an essential building block in applications such as source-synchronous interfaces and digital phase modulators. The resolution of DPCs using analog phase interpolators is severely affected by the operating frequency and rise times of the interpolator inputs. In this paper, we present a new DPC architecture that achieves high resolution independent of both the operating frequency and the rise time. The 8 phases generated by a phase-locked loop are dithered using a delta-sigma modulator to shape the truncation error to high frequency and is subsequently filtered using a delay-locked loop phase filter. The test chip, fabricated in a 0.13 mum CMOS process, operates from 0.5 -1.5 GHz and achieves a differential nonlinearity of less than plusmn0.1 ps and an integral nonlinearity of plusmn12 ps. The total power consumption while operating at 1 GHz is 15 mW.     

A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy

In this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and an all-digital PLL. The all-digital PLL design inherits the frequency response and stability characteristics of the analog prototype PLL     

Accurate Simulation of RF MEMS VCO performance including phase noise

A new coupled circuit and electrostatic/mechanical simulator (COSMO) is presented for the design of low phase noise radio frequency (RF) microelectromechanical systems (MEMS) voltage-controlled oscillators (VCOs). The numerical solution of device level equations is used to accurately compute the capacitance of a MEMS capacitor. This coupled with a circuit simulator facilitates the simulation of circuits incorporating MEMS capacitors. In addition, the noise from the MEMS capacitor is combined with a nonlinear circuit-level noise analysis to determine the phase noise of RF MEMS VCO. Simulations of two different MEMS VCO architectures show good agreement with experimentally observed behavior.     

Frequency detector for fast frequency lock of digital PLLs

A new frequency detector, which allows for a fast frequency lock of phase-locked loops (PLLs), is presented. It uses the feedback divider that already exists in a PLL to determine the frequency difference. The proposed frequency detector provides frequency difference information at each reference cycle, and thus guarantees fast frequency acquisition