High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/<3 nm) very high Ge fraction (/spl sim/ 80%) channel and Si cap (T/sub Si cap/<3 nm) have also been successfully fabricated on thin relaxed SOI substrates (T/sub SOI/=9 nm). The tradeoffs in obtaining a high-mobility (smaller bandgap) channel with low tunneling leakage on UT-SOI have been investigated in detail. The fabricated device shows very high mobility enhancements of >4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.     

Manufacturability of single and double-gate ultrathin silicon filmfully depleted SOI technologies

Of several possible devices that can be used for sub-70 nm node technologies, two are built on ultra thin SOI layers. Scaling of such thin silicon layer SOI devices is constrained by the severe short channel control problem. To alleviate this, double-gate structures have been proposed by Wong et al. (1999), Chang et al. (2000), and Ieong et al. (2000). In this paper, we assess the manufacturability of single-gate (SG) and symmetric double-gate (DG) devices for gate lengths between 15 and 70 nm. Our results show that SG devices are not only manufacturable but also have tighter distributions than DG devices; inverter ring oscillator (RO) stage delays and power consumption are also better for SG devices. Besides gate length we find two additional major sources of variation: silicon thickness and encapsulation width. We show that for an optimized double-gate device with minimized parasitic resistance, CD variations become a dominant factor at 20-nm gate lengths despite superior electrostatic integrity. Also, the work function of metal gates must be controlled to better than ±0.1 eV (3σ) to avoid severe manufacturability problems     

Complimentary single-electron/hole action of nanoscale SOI CMOS transistors

We propose a new device structure for room-temperature single-electron/hole transistors based on nanosize narrow-width fully depleted silicon-on-insulator (SOI) CMOS transistors. The floating body of SOI MOSFETs can become a Coulomb island, whose single charging energy is more than 30 meV, as the gate length and width of MOSFETs is less than 10 nm. As SOI MOSFETs are biased at accumulation, single-electron, or hole tunnels, are sent, one by one, from the source to the floating body and then to the drain via Zener tunneling process. N-channel SOI MOSFETs can have the functions of single-electron transistors (n-SETs) while p-channel MOSFETs can have the functions of single-hole transistors (p-SETs). SOI MOSFETs still behave as typical MOSFETs when biased at inversion. There is a gate voltage margin of 0.9 V to separate Coulomb blockade oscillations from CMOS normal operation.     

Mathematical Modelling of Cutting Force as the Most Reliable Information Bearer on Cutting Tools Wearing Phenomenon

Being one of their prominent exploitative characteristics, cutting tools durability depends on the character, intensity and the speed of wearing. Identification of tool wearing is of great significance for the purpose of avoiding sooner or later replacement of tools. The parameters of tool wearing can be measured by out-process and in-process-measuring systems. Given the extremely limiting role of the former in modern production lines, development of the latter （the indirect measuring systems） has gained prominence, The basis of indirect measuring systems comprises a set of various signals originating from the units of the system under treatment which stand in certain correlations with the wearing parameters. The paper presents mathematical models of axial force designed on the basis of experimental research in drilling tempered steel by twist drills made of high-speed steel manufactured by powder metallurgy.     

Intra-field effects on device and circuit manufacturability: astatistical simulation approach

In spite of the numerous improvements in deep ultraviolet (DUV) lithography, minimizing lens aberrations remains critical to obtaining manufacturable logic technologies. In this paper, we investigate the effects of lens imperfections on the distributions of process, device, and circuit parameters. Lens imperfections, as manifested by intrafield gate critical dimension (CD) variations, can affect device and circuit parameters strongly. The latter is central to designing fast high-yielding logic products, especially microprocessors. Our approach employs process, device, and statistical simulations, coupled with extensive calibration, to predict manufacturing distributions for a new technology well before it is ramped to full-scale production. We study nominal channel length n- and p-channel devices, inverter ring oscillators, and four-input NAND standard cells, We compare different stepper conditions both for conventional and annular illumination. We consider the case of more than one die in a reticle field and investigate how lens imperfections affects different dice therein. We apply our approach to an experimental DUV stepper and demonstrate coma effects that potentially lower yields. Our results also include a paradox: the best annular illumination case, which betters the CD distributions of conventional illumination, ultimately yields worse circuit performance     

Mechanism of electrical breakdown left of Paschen minimum

The breakdown mechanism of a gas at small PD values is considered. Comparing experimental results and theoretical analysis, the limits of different breakdown mechanisms are established. For SF₆ and Ar gases the conditions for streamer and those for the Townsend breakdown mechanism are found, as well as those for vacuum breakdown. The pressure values characteristic for avalanche and emission mechanisms of vacuum breakdown are obtained. Left from the Paschen minimum in the vicinity of the minimum point, edge-type breakdown is dominating, which currently is misinterpreted as an anomalous Paschen effect     

Manufacturability of 20-nm ultrathin body fully depleted SOI devices with FUSI metal gates

Ultrathin body (UTB) fully depleted silicon-on-insulator (FDSOI) devices show great performance due to undoped channels and excellent electrostatic control. Very high drive currents and good off-state leakage, ideal subthreshold slope, and small drain-induced barrier lowering (DIBL) have been reported with devices as short as 20 nm. The ultrathin channel enables high device performance, but it imposes a new set of problems. The control of the silicon thickness has become the dominant source of device variations. Selective epitaxial growth has become a necessity to achieve high performance and reliable contacts to UTB FDSOI devices. This work discusses silicon thickness control, selective epitaxial growth, and the mid-gap gate module needed for fully depleted devices. Very good control of short channel effect is shown and drive current fluctuations are discussed.