排序方式: 共有31条查询结果,搜索用时 0 毫秒
1.
Robin C.J. Wang C.C. Lee L.D. Chen Kenneth Wu K.S. Chang-Liao 《Microelectronics Reliability》2006,46(9-11):1673-1678
Microstructure effect of Cu/low-k interconnect, which is substantially affected by process condition or manufacturing deviation, is a dominated factors for copper stress and critical to the formation of stress-induced voiding (SIV). In this work, SIV at via bottom is studied in the aspects of thickness variation of copper interconnect and low-k dielectric. Besides, via-related factors consist of via profile and dimension are also involved in SIV sensitivity studies. With the assistance of finite element analysis (FEA), Cu stress in terms of different Cu/low-k microstructure scenarios are modelled to understand the voiding evolution and explore the their dependence with SIV susceptibility. Meanwhile, microstructure effects with and without redundant via are also simulated to evaluate their impacts on SIV immunity. 相似文献
2.
Zong-Hao Ye Kuei-Shu Chang-Liao Te-Chiang Liu Tien-Ko Wang Pei-Jer Tzeng Cha-Hsin Lin Min-Jinn Tsai 《Microelectronic Engineering》2009,86(7-9):1863-1865
Although enhancement in electrical properties of flash devices with HfO2 charge trapping layer has been reported, there are serious problems in retention characteristics. In this work, a novel SONOS-type flash device with TaN/Al2O3/HfO2/Si3N4/SiO2/Si structure is presented. Experimental results show that the program/erase speeds of the proposed devices can be enhanced by over one thousand times and the retention characteristic is improved as well. 相似文献
3.
Ping-Hung Tsai Kuei-Shu Chang-Liao Chu-Yung Liu Tien-Ko Wang Tzeng P.J. Lin C.H. Lee L.S. Tsai M.-J. 《Electron Device Letters, IEEE》2008,29(3):265-268
Operation properties of polysilicon-oxide-nitride-oxide-silicon-type Flash device with HfAlO charge-trapping layer having various Al contents were investigated in this letter. Satisfactory performance in terms of operation speed, retention, and program/erase endurance of the Flash device is achieved with the optimal Al content of 18%-28% in the HfAlO trapping layer. In addition, high-speed operation can be attained with the combination of channel-hot-electron-injection programming and band-to-band hot hole erasing for NOR architecture applications. 相似文献
4.
The photo-response of a ZnO nanoparticle embedded in a nanopore made on a silicon nitride membrane is investigated. The ZnO nanoparticle is manipulated onto the nanopore and sandwiched between aluminum contact electrodes from both the top and bottom. The asymmetric device structure facilitates current-voltage rectification that enables photovoltaic capacity. Under illumination, the device shows open-circuit voltage as well as short-circuit current. The fill factor is found to increase at low temperatures and reaches 48.6% at 100?K. The nanopore structure and the manipulation technique provide a solid platform for exploring the electrical properties of single nanoparticles. 相似文献
5.
Chien-Wei Liu Chin-Lung Cheng Kuei-Shu Chang-Liao Jin-Tsong Jeng Bau-Tong Dai Chen-Pang Tsai 《Microelectronic Engineering》2009,86(7-9):1692-1695
Silicon-oxide–nitride-oxide–silicon devices with nanoparticles (NPs) as charge trapping nodes (CTNs) are important to provide enhanced performance for nonvolatile memory devices. To study these topics, the TiOxNy metal oxide NPs embedded in the HfOxNy high-k dielectric as CTNs of the nonvolatile memory devices were investigated via the thermal synthesis using Ti thin-film oxidized in the mixed O2/N2 ambient. Well-isolated TiOxNy NPs with a diameter of 5–20 nm, a surface density of ~3 × 1011 cm?2, and a charge trap density of around 2.33 × 1012 cm?2 were demonstrated. The writing characteristic measurements illustrate that the memory effect is mainly due to the hole trapping. 相似文献
6.
Chin-Lung Cheng Chun-Yuan Lu Kuei-Shu Chang-Liao Ching-Hung Huang Sheng-Hung Wang Tien-Ko Wang 《Electron Devices, IEEE Transactions on》2006,53(1):63-70
Effects of the defects at high-/spl kappa/ dielectric/Si interface on the electrical characteristics of MOS devices are important issues. To study these issues, a low defect (denuded zone) at Si surface was formed by a high-temperature annealing in hydrogen atmosphere in this paper. Our results reveal that HfO/sub x/N/sub y/ demonstrates significant improvement on the electrical properties of MOS devices due to its low amount of the interstitial oxygen [O/sub i/] and the crystal-originated particles defects as well as small surface roughness at HfO/sub x/N/sub y//Si interface. The current-conduction mechanism of the HfO/sub x/N/sub y/ film at the low- and high-electrical field and high-temperature (T>100/spl deg/C) is dominated by Schottky emission and Frenkel-Poole (FP) emission, respectively. The trap energy level involved in FP conduction was estimated to be around 0.5eV. Reduced gate leakage current, stress-induced leakage current and defect generation rate, attributable to the reduction of defects at HfO/sub x/N/sub y//Si interface, were observed for devices with denuded zone. The variable rise and fall time bipolar-pulse-induced current technique was used to determine the energy distribution of interface trap density (D/sub it/). The results exhibit that relatively low D/sub it/ can be attributed to the reduction of defects at Si surface. By using denuded zone at the Si surface, HfO/sub x/N/sub y/ has demonstrated significant improvement on electrical properties as compared to SiO/sub x/N/sub y/. 相似文献
7.
Chin-Lung Cheng Kuei-Shu Chang-Liao Tzu-Chen Wang Tien-Ko Wang Howard Chih-Hao Wang 《Electron Device Letters, IEEE》2006,27(3):148-150
In this letter, the composition effects of hafnium (Hf) and tantalum (Ta) in Hf/sub x/Ta/sub y/N metal gate on the thermal stability of MOS devices were investigated. The work function of the Hf/sub x/Ta/sub y/N metal gate can reach a value of /spl sim/4.6 eV (midgap of silicon) by suitably adjusting the Hf and Ta compositions. In addition, with a small amount of Hf incorporated into a TaN metal gate, excellent thermal stability of electrical properties, including the work function, the equivalent oxide thickness, interface trap density and defect generation rate characteristics, can be achieved after a post-metal anneal up to 950/spl deg/C for 45 s. Experimental results indicate that Ta-rich Hf/sub x/Ta/sub y/N is a promising metal gate for advanced MOS devices. 相似文献
8.
Pei-Jer Tzeng Yi-Yuan Chang Kuei-Shu Chang-Liao 《Electron Device Letters, IEEE》2001,22(11):527-529
Plasma charging effects on the gate insulator of high-dielectric constant (k) material in MOS devices deserve to be investigated because of different trap-assisted conduction mechanisms. Plasma-induced degradation in gate-leakage current and time to breakdown is clearly observed in this work. MOS device with Si3N4 film seems to have smaller degradation of gate-leakage current while it suffers shorter time to breakdown as compared to Ta2O5 samples. For devices with Ta2O5 film, a larger physical thickness suffers more reliability degradation from plasma charging damage because of the richer traps. Thus, a smaller physical thickness of high-k dielectric film is favorable for sub-micron MOS devices of ULSI application 相似文献
9.
Haptic Direct-Drive Robot Control Scheme in Virtual Reality 总被引:3,自引:0,他引:3
Ming-Guo Her Kuei-Shu Hsu Tian-Syung Lan M. Karkoub 《Journal of Intelligent and Robotic Systems》2002,35(3):247-264
This paper explores the use of a 2-D (Direct-Drive Arm) manipulator for mechanism design applications based on virtual reality (VR). This article reviews the system include a user interface, a simulator, and a robot control scheme. The user interface is a combination of a virtual clay environment and human arm dynamics via robot effector handler. The model of the VR system is built based on a haptic interface device behavior that enables the operator to feel the actual force feedback from the virtual environment just as s/he would from the real environment. A primary stabilizing controller is used to develop a haptic interface device where realistic simulations of the dynamic interaction forces between a human operator and the simulated virtual object/mechanism are required. The stability and performance of the system are studied and analyzed based on the Nyquist stability criterion. Experiments on cutting virtual clay are used to validate the theoretical developments. It was shown that the experimental and theoretical results are in good agreement and that the designed controller is robust to constrained/unconstrained environment. 相似文献
10.
Chin-Lung Cheng Chien-Wei Liu Kuei-Shu Chang-Liao Ping-Hung Tsai Jin-Tsong Jeng Sung-Wei Huang Bau-Tong Dai 《Solid-state electronics》2008,52(10):1530-1535
The CoxNiyO hybrid metal oxide nanoparticles (HMONs) embedded in the HfOxNy high-k dielectric as charge trapping nodes of the nonvolatile memory devices have been formed via the chemical vapor deposition using the Co/Ni acetate calcined and reduced in the Ar/NH3 ambient. A charge trap density of 8.96 × 1011 cm?2 and a flatband voltage shift of 500 mV were estimated by the appearance of the hysteresis in the capacitance–voltage (C–V) measurements during the ±5 V sweep. Scanning electron microscopy image displays that the CoxNiyO HMONs with a diameter of ~10–20 nm and a surface density of ~1 × 1010 cm?2 were obtained. The mechanism related to the writing characteristics are mainly resulted from the holes trapping. Compared with those devices with the CoxNiyO HMONs formed by the dip-coated technique, memory devices with the CoxNiyO HMONs fabricated by the drop-coated technique show improved surface properties between the CoxNiyO HMONs and the HfON as well as electrical characteristics. 相似文献