An analytic expression of fmax for HBTs

An analytic expression of f_max is derived based on a practical HBT circuit model where collector junction capacitance is split up into internal and external parts. It shows that for advanced HBTs, f_max is well characterized by the product of the base resistance and internal collector capacitance. In other words, the external collector capacitance has only a small impact on the determination of f_max. Good agreement between experimental results and numerical circuit simulation confirms the validity of the HBT circuit model. The influence of the external collector capacitance on maximum available gain is also described     

Arsenic behavior in paddy fields during the cycle of flooded and non-flooded periods

The behavior of As in paddy fields is of great interest considering high As contents of groundwater in several Asian countries where rice is the main staple. We determined the concentrations of Fe, Mn, and As in soil, soil water, and groundwater samples collected at different depths down to 2 m in an experimental paddy field in Japan during the cycle of flooded and non-flooded periods. In addition, we measured the oxidation states of Fe, Mn, and As in situ in soil samples using X-ray absorption near-edge structure (XANES) and conducted sequential extraction of the soil samples. The results show that Fe (hydr)oxide hosts As in soil. Arsenic in irrigation waters is incorporated in Fe (hydr)oxide in soil during the non-flooded period, and the As is quickly released from soil to water during the flooded period because of reductive dissolution of the Fe (hydr)oxide phase and reduction of As from As(V) to As(III). The enhancement of As dissolution by the reduction of As is supported by high As/Fe ratios of soil water during the flooded period and our laboratory experiments where As(III) concentrations and As(III)/As(V) ratios in submerged soil were monitored. Our work, primarily based on data from an actual paddy field, suggests that rice plants are enriched in As because the rice grows in flooded paddy fields when mobile As(III) is released to soil water.     

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector

We describe a 40-Gbit/s-class clock and data recovery (CDR) circuit with an extremely wide pull-in range. A Darlington-type voltage-controlled oscillator (VCO) is newly designed to cover the STM-256/OC-768 full-rate-clock frequencies with a wide frequency margin. We also describe a new lock detector using an exclusive-NOR gate. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40-, 43-, and 45-Gbit/s PRBS with a word length of 2/sup 31/ - 1. We attached a frequency search and phase control (FSPC) circuit to the chip as a new frequency acquisition aid, and this allows the CDR circuit to pull in throughout a 39-45-Gbit/s range. The peak-to-peak and rms jitter of the recovered clock were 3.6 and 0.48 ps, respectively.     

Low-power 1:16 DEMUX and one-chip CDR with 1:4 DEMUX using InP-InGaAs heterojunction bipolar transistors

Using InP-InGaAs heterojunction bipolar transistor (HBT) technology, we have successfully designed and fabricated a low-power 1:16 demultiplexer (DEMUX) integrated circuit (IC) and one-chip clock and data recovery (CDR) with a 1:4 DEMUX IC for 10-Gb/s optical communications systems. The InP-InGaAs HBTs were fabricated by a nonself-aligned process for high uniformity of device characteristics and producibility. The 1:16 DEMUX IC and the one-chip CDR with the 1:4 DEMUX IC consist of approximately 1200 and 460 transistors, respectively. We have confirmed error-free operation at 10 Gb/s for all data outputs of both ICs. The 1:16 DEMUX IC and the one-chip CDR with the 1:4 DEMUX IC consume only 1 W and 950 mW, respectively. These results demonstrate the feasibility of InP-InGaAs HBTs for low power high-integration optical communication ICs.     

3.21 ps ECL gate using InP/InGaAs DHBT technology

A new circuit configuration for an emitter-coupled logic (ECL) gate that can reduce propagation delay time has been demonstrated. Nineteen-stage ring oscillators were fabricated using InP/InGaAs double-heterojunction bipolar transistors (DHBTs) with cutoff frequency f/sub T/ and maximum oscillation frequency f/sub max/ of about 232 and 360 GHz, respectively, to evaluate the speed performance of the proposed ECL gate. The minimum propagation delay is 3.21 ps/gate. The proposed ECL gate is about 8% faster than the conventional ECL gate.     

InP/InGaAs double-heterojunction bipolar transistor with step-graded InGaAsP collector

An MOCVD-grown InP/InGaAs double-heterojunction bipolar transistor with a step-graded InGaAsP collector is described. This transistor allows high injection current densities over 2.9*10/sup 5/ A/cm/sup 2/, which suggests no significant current blocking related to the wide-gap InP layers. A cutoff frequency of 155 GHz and a maximum oscillation frequency of 90 GHz are obtained at the collector current density of 1.6*10/sup 5/ A/cm/sup 2/.<>     

Syntheses and Photo-Reactions of N-Substituted Maleimide and Styrene Copolymers and their use as Photo-Resists

New synthetic routes for maleimide N-derivatives and N-oxy derivatives and their properties are described. The possibility of the utilization of the copolymers obtained from the maleimide derivatives and a vinyl monomer such as styrene in the field of photo-resists was examined. Together with the results obtained above. photochemical behaviour of the copolymers is also discussed in this paper.     

Effect of catch cup geometry on 3D boundary layer flow over the wafer surface in a spin coating

Recently, development of high technology has been required for the formation of thin uniform film in manufacturing processes of semiconductor as the semiconductor instruments become more sophisticated. Spin coating is usually used for spreading photoresist on a wafer surface. However, since rotating speed of the disk is very high in spin coating, the dropped photoresist scarers outward and reattaches on the film surface. A catch cup is set up outside the wafer in spin coating, and scattered photoresist mist is removed from the wafer edge by the exhaust flow generated at the gap between the wafer edge and the catch cup. In the dry process of a spin coating, it is a serious concern that the film thickness increases near the wafer edge in the case of low rotating speed. The purpose of this study is to make clear the effect of the catch cup geometry on the 3D boundary layer flow over the wafer surface and the drying rate of liquid film.     

High-bit-rate low-power decision circuit using InP-InGaAs HBT technology

We have successfully designed and fabricated a high-bit-rate low-power decision circuit using InP-InGaAs heterojunction bipolar transistors (HBTs). Its main design feature is the use of a novel master-slave D-type flip-flop (MS-DFF) as the decision circuit core to boost the operating speed. We achieved error-free operation at a data rate of up to 60 Gb/s using an undoped-emitter InP-InGaAs HBT with a cutoff frequency f/sub T/ of approximately 150 GHz and a maximum oscillation frequency f/sub max/ of approximately 200 GHz. Our decision circuit operates approximately 15% faster than one with a conventional MS-DFF core. We also achieved 90-Gb/s operation with low power consumption of 0.5 W using an InP-InGaAs DHBT exhibiting f/sub T/ and f/sub max/ of 232 and 360 GHz, respectively. These results demonstrate that InP-based HBTs and our novel MS-DFF are attractive for making ultrahigh-performance ICs for future optical communications systems operating at bit rates of 100 Gb/s or more.