Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits

The supply voltage to threshold voltage ratio is reduced with each new technology generation. The gate overdrive variation with temperature plays an increasingly important role in determining the speed characteristics of CMOS integrated circuits. The temperature-dependent propagation delay characteristics, as shown in this brief, will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of circuits in a 45-nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable operation under temperature fluctuations. A design methodology based on optimizing the supply voltage for temperature-variation-insensitive circuit performance is proposed in this brief. The optimum supply voltage is 45% to 53% lower than the nominal supply voltage in a 180-nm CMOS technology. Alternatively, the optimum supply voltage is 15% to 35% higher than the nominal supply voltage in a 45-nm CMOS technology. The speed and energy tradeoffs in the supply voltage optimization technique are also presented     

Domino logic with variable threshold voltage keeper

A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The variable threshold voltage keeper circuit technique enhances circuit evaluation speed by up to 60% while reducing power dissipation by 35% as compared to a standard domino (SD) logic circuit. The keeper size can be increased with the proposed technique while preserving the same delay or power characteristics as compared to a SD circuit. The proposed domino logic circuit technique offers 14% higher noise immunity as compared to a SD circuit with the same evaluation delay characteristics. Forward body biasing the keeper transistor is also proposed for improved noise immunity as compared to a SD circuit with the same keeper size. It is shown that by applying forward and reverse body biased keeper circuit techniques, the noise immunity and evaluation speed of domino logic circuits are simultaneously enhanced.     

Adsorption and Flotation Characteristics of the Different Types of Frothers

This article investigates the adsorption of different frothers onto talc particles. The adsorption and flotation characteristisc of tallow amine acetate (TAA) + frothers (MIBC and pine oil) was studied for talc mineral. In this study, we analyzed some parameters affecting froth flotation performance and it was determined that adsorption capacity in particular, had an important role in froth flotation enrichment. The effect of pH and adsorption time on adsorption capacity was also studied. Analyses were carried out using ultraviolet spectrometry. The results showed that MIBC had the lowest frother adsorption capacity and it improved recovery during froth flotation of on the talc. It can be said that MIBC was adsorbed on the talc surface less and provided the best conditions to generate bubbles in flotation cell.     

Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits

Circuits optimized for minimum energy consumption operate typically in the subthreshold regime with ultra-low power-supply voltages. Speed of a subthreshold logic circuit is enhanced with an increase in the die temperature. The excessive timing slack observed in the clock period of subthreshold logic circuits at elevated temperatures provides opportunities to lower the active-mode energy consumption. A temperature-adaptive dynamic-supply voltage-tuning technique is proposed in this paper to reduce the high-temperature energy consumption without degrading the clock frequency in ultra-low-voltage subthreshold logic circuits. Results indicate that the energy consumption can be lowered by up to 40% by dynamically scaling the supply voltage at elevated temperatures. An alternative technique based on temperature-adaptive reverse body bias to exponentially reduce the subthreshold leakage currents at elevated temperatures is also investigated. The active-mode energy consumption with two temperature-adaptive voltage-tuning techniques is compared. The impact of the process parameter and supply voltage variations on the proposed temperature-adaptive voltage scaling techniques is evaluated.     

Characterization of a Novel Nine-Transistor SRAM Cell

Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors are utilized for on-chip caches in today's high performance microprocessors. A new nine-transistor (9T) SRAM cell is proposed in this paper for simultaneously reducing leakage power and enhancing data stability. The proposed 9T SRAM cell completely isolates the data from the bit lines during a read operation. The read static-noise-margin of the proposed circuit is thereby enhanced by 2 X as compared to a conventional six-transistor (6T) SRAM cell. The idle 9T SRAM cells are placed into a super cutoff sleep mode, thereby reducing the leakage power consumption by 22.9% as compared to the standard 6T SRAM cells in a 65-nm CMOS technology. The leakage power reduction and read stability enhancement provided with the new circuit technique are also verified under process parameter variations.     

PARTICLE SIZE AND SHAPE CHARACTERISTICS OF KEMERBURGAZ QUARTZ SANDS OBTAINED BY SIEVING,LASER DIFFRACTION,AND DIGITAL IMAGE PROCESSING METHODS

The ever-progressing development of industrial processes and products regularly requires significant progress in the development of associated measurement techniques. With the advance of technology, there have been many developments in the mining sector. Mineral particle size is a critical parameter in any process involving the liberation and separation of minerals. In most mineral processing plants, product grade and mineral recovery require sufficient mineral liberation and optimum size distribution. There are many methods of measuring mineral particle sizes. Sieving, sedimentation, microscopy, digital image processing, and laser diffraction are the most common particle size analysis methods. The shape of the particles plays an important role in the assessment of particle size distribution. Most sizing techniques, however, assume that the sample being measured is spherical, as a sphere is the only shape that can be described by a single number. Therefore different techniques can give different results for the same sample depending on this aspect. Within the scope of this study, the particle size distribution of two different sand samples (Sarikum and Senkoy) was assessed by sieving, digital image processing, and laser diffraction techniques. In addition, the convexity and circularity parameters of the samples were measured by a Morphology G device. The particle size distribution results obtained from different techniques for each sample are discussed depending on the values of convexity and circularity of the sample particles.     

Adsorption and column flotation studies on talc using anionic and cationic collectors

Adsorption properties and column flotation were studied to investigate the interaction of the anionic and cationic collectors and flotation recoveries for talc mineral. Adsorption capacity is dependent on pH, adsorption time, temperature, collector concentration, and particle size. Langmuir adsorption model was suitable for describing isotherms. Analyses were carried out using UV spectrometry. In this study, we analyzed some parameters affecting column flotation performance. It was determined that adsorption capacity, especially, had an important role in column flotation enrichment.     

FinFET domino logic with independent gate keepers

Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the sub-threshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates these limitations by the excellent control over a thin silicon body by two electrically coupled gates. In this paper a variable threshold voltage keeper circuit technique using independent-gate FinFET technology is proposed for simultaneous power reduction and speed enhancement in domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The optimum independent-gate keeper gate bias conditions are identified for achieving maximum savings in delay and power while maintaining identical noise immunity as compared to the standard tied-gate FinFET domino circuits. With the variable threshold voltage double-gate keeper circuit technique the evaluation speed is enhanced by up to 49% and the power consumption is reduced by up to 46% as compared to the standard domino logic circuits designed for similar noise margin in a 32 nm FinFET technology.     

Low Power and High Speed Multi Threshold Voltage Interface Circuits

Employing multiple supply voltages (multi- V_DD) is an effective technique for reducing the power consumption without sacrificing speed in an integrated circuit (IC). In order to transfer signals among the circuits operating at different voltage levels specialized voltage interface circuits are required. Two novel multi-threshold voltage (multi-V_th) level converters are proposed in this paper. The new multi-V_th level converters are compared with the previously published circuits for operation at different supply voltages. When the circuits are individually optimized for minimum power consumption, the proposed level converters offer significant power savings of up to 70% as compared to the previously published circuits. Alternatively, when the circuits are individually optimized for minimum propagation delay, the speed is enhanced by up to 78% with the proposed voltage interface circuits in a 0.18- mum TSMC CMOS technology.     

Temperature-adaptive voltage scaling for enhanced energy efficiency in subthreshold memory arrays

Static random access memory (SRAM) circuits optimized for minimum energy consumption typically operate in the subthreshold regime with ultra low-power-supply voltages. Both the read and the write propagation delays of a subthreshold memory circuit are significantly reduced with an increase in the die temperature. The excessive timing slack observed in the clock period of constant-frequency subthreshold memory circuits at elevated temperatures provides new opportunities to lower the active-mode energy consumption. Temperature-adaptive dynamic supply voltage tuning (TA-DVS) technique is proposed in this paper to reduce the high-temperature energy consumption of ultra low-voltage subthreshold SRAM arrays. Results indicate that the energy consumption can be lowered by up to 32.8% by dynamically scaling the supply voltage at elevated temperatures. The impact of the temperature-adaptive dynamic supply voltage scaling technique on the data stability of the subthreshold SRAM bit-cells is presented. The effectiveness of the TA-DVS technique under process parameter and supply voltage variations is evaluated. An alternative technique based on temperature-adaptive reverse body bias (TA-RBB) to exponentially reduce the subthreshold leakage currents at elevated temperatures is also investigated. The active-mode energy consumption characteristics of the two temperature-adaptive voltage tuning techniques are compared.