Process study and optimization for fabrication of poly‐Si thin‐film transistors on plastic substrates

Abstract— A complete poly‐Si thin‐film transistor (TFT) on plastic process has been optimized to produce TFT arrays for active‐matrix displays. We present a detailed study of the poly‐Si crystallization process, a mechanism for protecting the plastic substrate from the pulsed laser used to crystallize the silicon, and a high‐performance low‐temperature gate dielectric film. Poly‐Si grain sizes and the corresponding TFT performance have been measured for a range of excimer‐laser crystallization fluences near the full‐melt threshold, allowing optimization of the laser‐crystallization process. A Bragg reflector stack has been embedded in the plastic coating layers; its effectiveness in protecting the plastic from the excimer‐laser pulse is described. Finally, we describe a plasma pre‐oxidation step, which has been added to a low‐temperature (<100°C) gate dielectric film deposition process to dramatically improve the electrical properties of the gate dielectric. These processes have been integrated into a complete poly‐Si TFT on plastic fabrication process, which produces PMOS TFTs with mobilities of 66 cm² /V‐sec, threshold voltages of ?3.5 V, and off currents of approximately 1 pA per micron of gate width.     

Transient behavior of adjustable threshold a-Si:H/a-SiC:Hthree-color detector

In this paper, we investigate the transient behavior of a-Si:H/a-SiC:H adjustable-threshold three-color detectors (ATCDs) for applications in bidimensional large area image sensors. Red, green, and blue color sensing in the charge integration regime is demonstrated, and the transient mechanisms of charge and discharge of the equivalent capacitance are discussed by means of load curve diagrams. The possibility of driving 2-D arrays of ATCDs is discussed by means of a test circuit simulating the row select TFT and the data line capacitance by discrete components. Readout times on the microsecond timescale and saturation times three orders of magnitude greater have been obtained under 0.1 mW/cm² illumination, resulting in the possibility of scanning 1000 rows. Finally, an equivalent circuit is introduced and solved by AIM-SPICE, and simulations of the static and dynamic behavior are presented     

Hybrid integration of GaAs-based VCSEL array with amorphous silicon sensor

We describe an optoelectronic module incorporating a vertical-cavity surface-emitting laser (VCSEL) array with a semitransparent light monitor. The power monitor is a p-i-n amorphous silicon photodetector fabricated on glass. Sets of micromachined springs for electrical contacting are also fabricated in the same process on the same glass substrate. Hybrid packages are formed by pressing the compliant springs against individual contact pads of the GaAs VCSEL array in a flip-chip assembly process. The light sensor is aligned directly on top of the laser elements. Most of the laser light is transmitted through the sensor, yet a large dynamic range is maintained because of the sensors exceedingly low dark current.     

High-performance TFTs fabricated on plastic substrates

Poly-Si thin-film transistors (TFTs) have recently been introduced to commercial glass flat-panel displays. This letter presents a manufacturable process for fabricating poly-Si TFTs directly on plastic substrates that exceed TFT parameter requirements for active-matrix displays. Plastic sheets are laminated onto carrier wafers, to allow use of automated tools for manufacturing. In order to maintain adhesion through the whole process, the wafer temperature is kept below 105/spl deg/C. Laser crystallization is used to grow poly-Si, and a quarter-wavelength stack layer is deposited to protect plastic from the laser processing. In order to achieve state-of-the-art poly-Si TFTs on plastic, the gate oxide is optimized. Using a higher temperature anneal after delamination minimizes leakage currents.     

Low pinch-off voltage amorphous silicon junction field-effect transistor: experiment and simulation

In this work, a junction field effect transistor (JFET) based on a-Si:H is presented. The drain-source contacts are made on top of the n-layer of a glass/metal/p/sup +/-i-n structure. The channel conductivity can be modulated by a reverse bias applied to the p/sup +/-i-n junction, which varies the depth or the length of the depletion region. In amorphous silicon, the depletion of doped layers is limited by the high defect density induced by the doping process. Here, the electron concentration of the n-doped layer (the device channel) in a p-i-n amorphous silicon junction is studied by using a one-dimensional finite-difference simulator. The n-channel conductivity is then obtained by integrating the free electron concentration along the drain-source direction. Pinch-off regime is achieved when the n-layer is fully depleted. A JFET with W/L = 400 /spl mu/m/40 /spl mu/m was fabricated. Transistors with pinch-off voltages around -3.6 V and transconductance values of the order of 10/sup -7/ A/V were obtained. Comparison between experimental and modeled output characteristics suggests the presence of a defect-rich layer at the channel-air interface. This is related to the damage induced by the process steps during the device fabrication. The achieved experimental results make the device suitable for applications in linear circuits. In particular, unlike thin film transistors (TFTs), JFETs do not require high-temperature, high-quality dielectric layers, and appear particularly attractive for process on plastic substrates.