Analysis of stepwise charging limits and its implementation for efficiency improvement in switched capacitor DC–DC converters

In this work we analysed the stepwise charging technique to find the limits from which it is beneficial in terms of load capacitance and charge–discharge frequency. We included in the analysis practical limitations such as the consumption of auxiliary logic needed to implement the technique and the minimum size of auxiliary switches imposed by the technology. We proposed an ultra-low-power logic block to push these limits and to obtain benefits from this technique in small capacitances. Finally, we proposed to use a stepwise driver in the driving of the gate capacitance of power switches in switched-capacitor (SC) DC–DC converters. We designed and manufactured, in a 130 nm process, a SC DC–DC converter and measured a 29% energy reduction in the gate-drive losses of the converter. This accounts for an improvement of 4% (from 69 to 73%) in the overall converter efficiency.

     

Signal probability for reliability evaluation of logic circuits

As integrated circuits scale down into nanometer dimensions, a great reduction on the reliability of combinational blocks is expected. This way, the susceptibility of circuits to intermittent and transient faults is becoming a key parameter in the evaluation of logic circuits, and fast and accurate ways of reliability analysis must be developed. This paper presents a reliability analysis methodology based on signal probability, which is of straightforward application and can be easily integrated in the design flow. The proposed methodology computes circuit’s signal reliability as a function of its logical masking capabilities, concerning multiple simultaneous faults occurrence.     

Design of Down-Sampling Processors for Radio Communications

This paper deals with design and implementation of digital filter processors to be used as down-samplers in wireless transceivers. We consider a homodyne direct conversion and propose an improved method to specify each stage of the cascade structure. The proposed scheme results in a globally compact implementation. The method is detailed for DECT standard and illustrated by a fixed point FPGA based implementation.     

Analog to digital conversion: technical aspects

An ideal radio communication receiver places the analog to digital conversion just after the antenna. It is an objective in a “software radio” perspective. The available silicon technologies do not provide the performance required by this application. We are able to evaluate the present limits and the gap between these limits and the ideal solution proposed. In this paper, we describe the present possibilities in terms of receiver architectures and we deduce theAdc specifications. Then we analyse differentAdc architectures adapted to this application. The choice is mainly between pipeline and sigma- deltaAdc. We compare them in terms of power consumption and we introduce a factor of merit. The future technologies will have an impact onAdc performance. Superconductor technology applied toAdc may be a solution and it is analysed at the end of this paper.     

A survey of in-spin transfer torque MRAM computing

Science China Information Sciences -     

Yield and reliability issues in nanoelectronic technologies

Integrated circuits have known a constant evolution in the last decades, with increases in density and speed that follow the rates predicted in Moore’s law. The tradeoffs in area, speed and power, allowed by theCmos technology, and its capacity to integrate analog, digital and mixed components, are key features to its dissemination in the telecommunications field. In fact, the progress of theCmos technology is an important driver for telecommunications evolution, with the continuous integration of complex functions needed by demanding applications. As integrated circuits evolve, they approach some limits that make further improvements more difficult and even unpredictable. With deep-submicron structures, the yield of manufacturing processes is one of the main challenges of the semiconductor industry, with negative impacts on time-to-market and profitability. With reduced voltages and increased speed and density, the reliability of deep-submicron circuits is another concern for designers, since noise immunity is reduced and thermal noise effects show-up. In this paper we present an overview of the issues related with the scaling of integrated circuits into nanometer technologies, detailing the yield and reliability problems. We present the state of the art in proposed solutions and alternatives that can improve the chances of a large utilization of these nanotechnologies.     

Optimal digital reconstruction and calibration for multichannel Time Interleaved ΣΔ ADC based on Comb-filters

High resolution, large dynamic range wideband Analog to Digital Converter (ADC) remains a bottleneck to realize software and cognitive radio receivers. Time Interleaved Sigma-Delta (TIΣΔ) architecture is a potential candidate to increase the bandwidth of the ΣΔ like ADCs. However, very high digital filter complexity is required and it is very sensitive to channel mismatch which is unavoidable especially in advanced manufacturing process. This paper proposes a new digital signal processing based on Comb-filter cells and correction FIR filter. Comparing to existing solutions, the proposed solution reduces Drastically the digital filter complexity and thus the power consumption and the die area of the digital post-filtering at the backend of the TIΣΔ ADC. This solution was validated and synthesized in a 1.2 V, 65 nm CMOS process using VHDL language. The total die area is estimated to 0.115 mm². Moreover, this paper proposes a fully digital gain equalization and offset cancellation methods without any additional material resources. These methods achieve a high accuracy with a very short calibration time estimated to about 10 clock cycles.     

Progressive module redundancy for fault-tolerant designs in nanoelectronics

Redundancy techniques are widely used to increase the reliability of the circuits. This paper proposes an efficient method to select the best subset among possible redundant architectures. It builds upon the progressive module redundancy technique and the block grading concept. Furthermore, this method is not constrained on TMR but extends to 5MR. Experiment results demonstrate its advantages in efficiency, reliability and cost. The proposed method points out a new direction of economical redundant fault-tolerant designs for nanoelectronics.