Remote Didactic Laboratory “G. Savastano,” The Italian Experience for E-Learning at the Technical Universities in the Field of Electrical and Electronic Measurements: Overview on Didactic Experiments

The Remote Didactic Laboratory Laboratorio Didattico Remoto - LA.DI.RE. ldquoG. Savastanordquo is the e-learning measurement laboratory supported by the Italian Ministry of Education and University. It involves about 20 Italian universities and provides students of electric and electronic measurement courses with access to remote measurement laboratories delivering different didactic activities related to measurement experiments. In order to demonstrate the versatility for didactic use, the overview of some experiments is given. The didactic experiments summarized in this paper concern measurement characterization of instruments and communication systems, measurement devices for remote laboratories, basic electrical measurements, magnetic measurements, electromagnetic-interference measurements, and signal processing for measurement applications.     

Minimizing memory access energy in embedded systems by selective instruction compression

We propose a technique for reducing the energy spent in the memory-processor interface of an embedded system during the execution of firmware code. The method is based on the idea of compressing the most commonly executed instructions so as to reduce the energy dissipated during memory access. Instruction decompression is performed on-the-fly by a hardware block located between processor and memory: No changes to the processor architecture are required. Hence, our technique is well suited for systems employing IP cores whose internal architecture cannot be modified. We describe a number of decompression schemes and architectures that effectively trade off hardware complexity and static code size increase for memory energy and bandwidth reduction, as proved by the experimental data we have collected by executing several test programs on different design templates.     

Discrete-time battery models for system-level low-power design

For portable applications, long battery lifetime is the ultimate design goal. Therefore, the availability of battery and voltage converter models providing accurate estimates of battery lifetime is key for system-level low-power design frameworks. In this paper, we introduce a discrete-time model for the complete power supply subsystem that closely approximates the behavior of its circuit-level continuous-time counterpart. The model is abstract and efficient enough to enable event-driven simulation of digital systems described at a very high level of abstraction and that includes, among their components, also the power supply. The model gives the designer the possibility of estimating battery lifetime during system-level design exploration, as shown by the results we have collected on meaningful case studies. In addition, it is flexible and it can thus be employed for different battery chemistries     

Power optimization of core-based systems by address bus encoding

This paper presents a solution to the problem of reducing the power dissipated by a digital system containing an intellectual proprietary core processor which repeatedly executes a special-purpose program. The proposed method relies on a novel, application-dependent low-power address bus encoding scheme. The analysis of the execution traces of a given program allows an accurate computation of the correlations that may exist between blocks of bits in consecutive patterns; this information can be successfully exploited to determine an encoding which sensibly reduces the bus transition activity. Experimental results, obtained on a set of special-purpose applications, are very satisfactory; reductions of the bus activity up to 64.8% (41.8% on average) have been achieved over the original address streams. In addition, data concerning the quality and the performance of the automatically synthesized encoding/decoding circuits, as well as the results obtained for a realistic core-based design, indicate the practical usefulness of the proposed power optimization strategy     

Implementation of a thermal management unit for canceling temperature-dependent clock skew variations

Thermal gradients across the die are becoming increasingly prominent as we scale further down into the sub-nanometer regime. While temperature was never a primary concern, its non-negligible impact on delay and reliability is getting significant attention lately.One of the principal factors affecting designs today is timing criticality, which, in today's technologies is mostly determined by wire delays. Clocks, which are the backbone of the interconnect network, are extremely prone to temperature dependent delay variations and need to be designed with extreme care so as to meet accurate timing constraints. Their skew has to be minimized in order to guarantee functionality, albeit in the presence of these process variations.Temperature, on the other hand, is dynamic in nature and its effects hence need run-time monitoring and management. One of the most efficient ways to manage temperature dependent skew is through the use of buffers with dynamically tunable delays. The use of such buffers in the clock distribution network allows modulating the delay on selected branches of the clock network based on a thermal profile, so as to keep the skew within acceptable bounds.A runtime scheme obviously requires an on-line management unit. Our work predominantly focuses on the implementation of one such unit, while studying its impact on design parameters such as area, wire-length and power. Results show negligible a impact (0.67% in area, 0.62% in wire-length, 0.33% in power, and 0.37% in via-number) on the design.     

Energy saving in existing buildings by an intelligent use of interoperable ICTs

In this paper, we report a methodology, developed in the context of Smart Energy Efficient Middleware for Public Spaces European Project, aimed at exploiting ICT monitoring and control services to reduce energy usage and CO₂ footprint in existing buildings. The approach does not require significant construction work as it is based on commercial-off-the-shelf devices and, where present, it exploits and integrates existing building management systems with new sensors and actuator networks. To make this possible, the proposed approach leverages upon the following main contributions: (a) to develop an integrated building automation and control system, (b) to implement a middleware for the energy-efficient buildings domain, (c) to provide a multi-dimensional building information modelling-based visualisation, and (d) to raise people’s awareness about energy efficiency. The research approach adopted in the project started with the selection, as case studies, of representative test and reference rooms in modern and historical buildings chosen for having different requirements and constraints in term of sensing and control technologies. Then, according to the features of the selected rooms, the strategies to reduce the energy consumptions were defined, taking into account the potential savings related to lighting, heating, ventilation, and air conditioning (HVAC) systems and other device loads (PC, printers, etc.). The strategies include both the control of building services and devices and the monitoring of environmental conditions and energy consumption. In the paper, the energy savings estimated through simulation, for both HVAC and lighting, are presented to highlight the potential of the designed system. After the implementation of the system in the demonstrator, results will be compared with the monitored data.     

An open distributed measurement system based on an abstract client-server architecture

This paper describes in detail a Java-based, client-server architecture specifically designed to allow a flexible management of remote instruments. The main attributes of the proposed solution are portability and extensibility. The former feature is assured by the employment of the TCP/IP protocol suite and by the Java language properties. The latter is due to the high level of abstraction of the system implementation. This approach addresses a wide range of possible applications with high code reusability. In fact, the proposed architecture permits to drive many kinds of different devices and can be easily upgraded simply by adding a limited amount of code on the server computer whenever a new instrument is connected to the system.     

Cellular-automata models for reliability analysis of systems onsilicon

Reliability issues are important during the design of VLSI integrated circuits built on silicon, due to several design constraints-higher performance and frequency, device miniaturization, higher levels of on-chip integration-that must be satisfied by the final product. Digital designs are usually subject to failures due to the increased operating temperature caused by their high power dissipation. This paper addresses the problem of analyzing the reliability with respect to power consumption of digital systems constructed with CMOS technology. The solution is simulation-based, and relies on a new, cellular automaton-based model which is particularly suitable for identifying the power characteristics of a sequential design. The model is discussed in detail; it provides a homogeneous representation of all the components of the circuit. Primary inputs, flip-flops, primary outputs, and their related cones of combinational logic are modeled in the same way by means of cellular automaton cells. The model is used to analyze reliability of sequential VLSI circuits. To prove the applicability of the model, we report experimental results on some standard benchmarks taken from the literature     

Increasing energy efficiency of embedded systems byapplication-specific memory hierarchy generation

This article presents a methodology for automatic memory hierarchy generation that exploits memory access locality of embedded software. The methodology is successfully applied to the design of an MP3 decoder