Algebraic integer architecture with minimum adder count for the 2-D Daubechies 4-tap filters banks

A multiplierless architecture based on algebraic integer representation for computing the Daubechies 4-tap wavelet transform for 1-D/2-D signal processing is proposed. This architecture improves on previous designs in a sense that it minimizes the number of parallel 2-input adder circuits. The algorithm was achieved using numerical optimization based o exhaustive search over the algebraic integer representation. The proposed architecture furnishes exact computation up to the final reconstruction step, which is the operation that maps the exactly computed filtered results from algebraic integer representation to fixed-point. Compared to Madishetty et al. (IEEE Trans Circuits Syst I (Accepted, In Press), 2012a), this architecture shows a reduction of \(10\cdot n-3\) adder circuits, where \(n\) is the number of wavelet decomposition levels. Standard \(512\times 512\) images Mandrill, Lena, and Cameraman were submitted to digital realizations of both proposed algebraic integer based as well as fixed-point schemes, leading to quantifiable comparisons. The design is physically implemented for a 4-level 2-D decomposition using a Xilinx Virtex-6 vcx240t-1ff1156 FPGA device operating at up to a maximum clock frequency of 263.15 MHz. The FPGA implementation is tested using hardware co-simulation using an ML605 board with clock of 100 MHz. A 45 nm CMOS synthesis shows improved clock frequency of better than 500 MHz for a supply voltage of 1.1 V.     

Massively parallel systolic‐array architectures for 2d IIR polyphase space–time plane‐wave beam digital filters

A systolic architecture has recently been proposed for implementing two‐dimensional infinite impulse response (IIR) space–time beam plane‐wave filters at a throughput of one‐frame‐per‐clock–cycle for such applications as real‐time broadband smart antennas. A novel polyphase systolic architecture is proposed here that further increases the throughput of these IIR beam filters, by a factor of M, to M‐frames‐per‐clock‐cycle, where M is the number of polyphases. The proposed method combines the polyphase approach, along with pipelining and look‐ahead optimization methods, to achieve frame sample frequencies that are several times higher than the clock‐cycle limit of the very large‐scale integration (VLSI) technology, thereby potentially allowing multi‐GHz frame sample frequencies using current custom VLSI circuits. The implementation of a field programmable gate array‐based real‐time prototype is described, tested and verified for the two‐phase case (M = 2) at a technology‐limited clock frequency of 50 MHz which corresponds to a throughput of 100 million‐frames‐per‐clock–cycle. Copyright © 2010 John Wiley & Sons, Ltd.     

A Systolic-Array Architecture for First-Order 3-D IIR Frequency-Planar Filters

A massively parallel systolic-array architecture is proposed for the implementation of real-time VLSI spatio-temporal 3-D IIR frequency-planar filters at a throughput of one-frame-per-clock-cycle (OFPCC). The architecture is based on a differential-form transfer function and is of low circuit complexity compared with the direct-form architecture. A 3-D look-ahead (LA) form of the transfer function is proposed for maximizing the speed of the implementation, which has a nonseparable 3-D transfer function. The systolic array enables real-time implementation of 3-D IIR frequency-planar filters at radio-frequency (RF) frame-rates and is therefore a suitable building block for 3-D IIR digital filters having beam- and cone-shaped passbands as required for smart-antenna-array beam-forming applications involving the broadband spatio-temporal filtering of plane-waves. The fixed-point systolic-array implementation have a throughput of OFPCC and the tested real-time prototype achieves frame (clock) sample frequencies of up to 90 MHz using one Xilinx Virtex-4 sx35-10ff668 FPGA device.      

Wide‐band aperture array using a four‐channel manifold‐type planar multiplexer and digital 2‐D IIR filterbank

Emerging wide‐band communications and spectrum‐sensing systems demand support for multiple electronically scanned beams while maintaining a frequency independent, constant far‐field beam width. Realizing existing phased‐array technology on a digital scale is computationally intensive. Moreover, digitizing wide‐band signals at Nyquist rate requires complex high‐speed analog‐to‐digital converters (ADCs), which is challenging for real developments driven by the current ADC technology. A low‐complexity alternative proposed in this paper is the use of radio‐frequency (RF) channelizers for spectrum division followed by sub‐sampling of the RF sub‐bands, which results in extensive reduction of the necessary ADC operative frequency. The RF‐channelized array signals are directionally filtered using 2‐D digital filterbanks. This mixed‐domain RF/digital aperture array allows sub‐sampling, without utilizing multi‐rate 2‐D systolic arrays, which are difficult to realize in practice. Simulated examples showing 14–19 dB of rejection of wide‐band interference and noise for a processed bandwidth of 1.6 GHz are demonstrated. The sampling rate is 400 MHz. The proposed VLSI hardware uses a single‐phase clock signal of 400 MHz. Prototype hardware realizations and measurement using 65‐nm Xilinx field‐programmable gate arrays, as well as Cadence RTL synthesis results including gate counts, area‐time complexity, and dynamic power consumption for a 45‐nm CMOS circuit operating at B _DC = 1.1 V, are presented. Copyright © 2016 John Wiley & Sons, Ltd.     

2D space–time wave-digital multi-fan filter banks for signals consisting of multiple plane waves

Two dimensional space–time fan filters may be used for the highly-selective enhancement of spatio-temporal plane-waves on the basis of their directions of arrival. Unlike uniform bandwidth beam filters, ideal fan filters transmit passband signals over a range of directions of arrival that is independent of their 1D temporal spectrum. In this work, closed-form 2D wave-digital filter design equations and corresponding hardware architectures are proposed for realizing M independent fan-shaped passbands having independently steerable directionality and selectivity. A design method based on LCR ladder networks is proposed and implemented using a 2D time-multiplexed raster-scanned architecture that is suitable for low frequency applications such as audio, multimedia, seismic and ultrasonic beamforming. The architectures are designed, simulated, physically realized and tested on FPGA-based prototypes. Examples of 2D IIR M-fan filterbanks with FPGA implementations, together with measured results from on-chip hardware verifications, show the successful design and hardware realization. The filterbanks and hardware architectures are shown to be suitable for real-time sensor-array beamforming applications using custom VLSI circuits.     

Applications of RF aperture-array spatially-bandpass 2-D IIR filters in sub-Nyquist spectrum sensing,wideband doppler radar and radio astronomy beamforming

The application of two-dimensional (2-D) infinite impulse response (IIR) spatially-bandpass (SBP) filters as a digital beamformer for a wide spectrum of practical applications spanning wireless cognitive radio communications, doppler radar, and radio astronomy instrumentation is discussed. The paper starts with an introduction of the recently proposed 2-D SBP filter. The first application is a spectrum sensing scheme for dynamic spectrum access based cognitive radios. A 2-D IIR SBP filter is used in conjunction with a sub-Nyquist wideband signal reconstruction technique to achieve aperture-array directional spectrum sensing using sub-Nyquist sparse sampling based on the recently reported Eldar algorithm. The second application is related to wideband pulse and continuous-wave frequency modulated Doppler radar sensing. The SBP filter is integrated with a wideband radar back-end connected to an electronically-steerable aperture antenna. A a low-complexity directional localization algorithm is presented, which estimates the range and angle of a target scatterer with a signal to interference ratio improvement of 10 dB. We also present applications of 2-D IIR SBP in the fields of classification and remote sensing of unmanned aerial vehicles. Finally, a digital aperture-array wideband beamforming model using the 2-D IIR SBP filters is presented for radio telescope systems based on dense aperture arrays and time-domain beamforming. A well-known example is the study of pulsar astrophysics using a highly-directional aperture antenna system. The 2-D IIR SBP beamformer is simulated as the digital backend of the time-domain beamforming system with array signals synthesized using measured time-domain signatures from the Crab pulsar obtained from the GAVRT. The SBP filter shows a gain of 12.3 dB with an order of magnitude lower circuit complexity compared to traditional phased-array digital beamformers. To obtain comparable levels of SINR improvement, the wideband phased-array beamformers require 48-point FFTs per antenna. Assuming the optimum three real-multiplications per complex multiplication for the Gauss algorithm, it is discovered that the proposed 2-D IIR SBP beamformers are more than 97 % lower in digital multiplier complexity compared to traditional FIR phased-array FFT-beamformers.     

Energy-Efficient 8-Point DCT Approximations: Theory and Hardware Architectures

Due to its remarkable energy compaction properties, the discrete cosine transform (DCT) is employed in a multitude of compression standards, such as JPEG and H.265/HEVC. Several low-complexity integer approximations for the DCT have been proposed for both 1D and 2D signal analyses. The increasing demand for low-complexity, energy-efficient methods requires algorithms with even lower computational costs. In this paper, new 8-point DCT approximations with very low arithmetic complexity are presented. The new transforms are proposed based on pruning state-of-the-art DCT approximations. The proposed algorithms were assessed in terms of arithmetic complexity, energy retention capability, and image compression performance. In addition, a metric combining performance and computational complexity measures was proposed. Results showed good performance and extremely low computational complexity. Introduced algorithms were mapped into systolic-array digital architectures and physically realized as digital prototype circuits using FPGA technology and mapped to 45 nm CMOS technology. All hardware-related metrics showed low resource consumption of the proposed pruned approximate transforms. The best proposed transform according to the introduced metric presents a reduction in power consumption of 21–25 %.     

Effects of Quantization in Systolic 2D IIR Beam Filters on UWB Wireless Communications

Ultra-wideband (UWB) wireless beamforming systems may potentially be implemented digitally at multi-gigahertz clock frequencies using low-precision systolic array realizations of two-dimensional (2D) infinite impulse response (IIR) beam plane-wave filters. The finite precision performance of such filters is analyzed in terms of quantization noise. Extensive Monte Carlo simulations are performed using test vectors that are derived from 2D finite-difference time-domain (FDTD) computational electromagnetic models of the UWB channels. The bit error rate (BER) is determined as a function of signal-to-interference ratio (SIR), with and without beamforming, and for various practical combinations of finite internal wordlengths and A/D converter precisions. It is established that 3-bit A/D converters with 3- to 6-bit internal wordlengths are adequate for good performance and that 4-bit A/D converters with 4- to 7-bit internal wordlengths achieve excellent performance.