Precise delay generation using coupled oscillators

A new delay generator based on a series of coupled ring oscillators has been developed; it produces precise delays with subgate delay resolution for chip testing applications. It achieves a delay resolution equal to a buffer delay divided by the number of rings. The coupling employed forces the outputs of a linear array of ring oscillators oscillating at the same frequency to be uniformly offset in phase by a precise fraction of a buffer delay. The buffer stage used in the ring oscillators is based on a source-coupled pair and achieves high supply noise rejection while operating at low supply voltages. Experimental results from a 2-μm N-well CMOS implementation of the delay generator demonstrate that it can achieve an output delay resolution of 101 ps while operating at 141 MHz with a peak error of 58 ps     

Low-jitter process-independent DLL and PLL based on self-biasedtechniques

Delay-locked loop (DLL) and phase-locked loop (PLL) designs based upon self-biased techniques are presented. The DLL and PLL designs achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and, most importantly, low input tracking jitter. Both the damping factor and the bandwidth to operating frequency ratio are determined completely by a ratio of capacitances. Self-biasing avoids the necessity for external biasing, which can require special bandgap bias circuits, by generating all of the internal bias voltages and currents from each other so that the bias levels are completely determined by the operating conditions. Fabricated in a 0.5-μm N-well CMOS gate array process, the PLL achieves an operating frequency range of 0.0025 MHz to 550 MHz and input tracking jitter of 384 ps at 250 MHz with 500 mV of low frequency square wave supply noise     

Evaluation of the safety and efficacy of ketorolac versus morphine by patient-controlled analgesia for postoperative pain

STUDY OBJECTIVE: To compare ketorolac tromethamine with morphine for pain management after major abdominal surgery. DESIGN: Double-blind, randomized study. SETTING: Hospital recovery room and postoperative surgical unit. PATIENTS: One hundred ninety-one patients with at least moderate pain after major abdominal surgery. INTERVENTIONS: Patients received ketorolac by patient-controlled analgesia (PCA) bolus alone (Ket B), ketorolac by bolus plus infusion (Ket I), or morphine by PCA bolus (morphine), with injectable morphine available for supplementation. MEASUREMENTS AND MAIN RESULTS: Levels of sedation, pain intensity, pain relief, and adverse events were recorded at baseline, at 2, 4, and 6 hours, and at termination. Supplemental morphine was required by 71% of Ket B patients, 67% of Ket I patients, and 38% of morphine patients (p < or = 0.001 for Ket B vs morphine). Although patients receiving ketorolac required more supplemental morphine than the morphine group (6.0 mg Ket I, 6.2 mg Ket B, 4.0 mg morphine), there was a large morphine-sparing effect in both ketorolac groups (total morphine 6.0 mg Ket I, 6.2 mg Ket B, 33.3 mg morphine). Overall pain relief scores were similar for morphine and Ket I groups, and were lower for Ket B than for morphine (p = 0.002). There were no differences among groups in numbers of patients with adverse events. CONCLUSION: Ketorolac may be effective when administered by PCA device, and has a clear morphine-sparing effect.     

Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL

A self-biased phase-locked loop (PLL) uses a sampled feedforward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of multiplication factor, output frequency, process, voltage, and temperature. The PLL achieves a multiplication range of 1-4096 with less than 1.7% output jitter. Fabricated in 0.13-/spl mu/m CMOS, the area is 0.182mm/sup 2/ and the supply is 1.5 V.