Stress voltage polarity dependence of JVD-Si/sub 3/N/sub 4/ MNSFET degradation

In this paper, we study the stress voltage polarity-dependent reliability of n-channel metal-nitride-silicon field-effect transistors (MNSFETs) with ultrathin jet vapor deposited (JVD) silicon nitride dielectric. Under constant voltage stress, device parameters such as threshold voltage and transconductance degrade. Charge trapping due to interface and bulk traps is observed. Our study shows that the degradation is polarity dependent. MNSFETs show lower degradation under positive stress fields. We have also compared the performance of MNSFETs with conventional MOSFETs under identical stress conditions. Under positive stressing, MNSFETs clearly outperform MOSFETs, but under negative stressing, MNSFETs show more degradation.     

A new method to characterize border traps in submicron transistors using hysteresis in the drain current

In this paper, a new method for measuring border trap density (n/sub BT/) in submicron transistors using hysteresis in the drain current is proposed. This method is used to measure energy and spatial distribution of border traps in jet vapor deposited (JVD) metal-silicon nitride-semiconductor field effect transistors (MNSFETs). The drain current transient varies linearly with logarithmic time suggesting that tunneling to and from the spatially uniform border traps is the dominant charge exchange mechanism. Using a feedback mechanism gate voltage transients are obtained from which n/sub BT/ is calculated. The prestress energy distribution in JVD MNSFETs is found to be uniform whereas the post-stress energy distribution shows a peak near the midgap.