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A fully integrated 0.18-/spl mu/m CMOS direct conversion receiver front-end with on-chip LO for UMTS
This paper presents a 0.18-/spl mu/m CMOS direct-conversion IC realized for the Universal Mobile Telecommunication System (UMTS). The chip comprises a variable gain low-noise amplifier, quadrature mixers, variable gain amplifiers, and local oscillator generation circuits. The solution is based on very high dynamic range front-end blocks, a low-power superharmonic injection-locking technique for quadrature generation and continuous-time dc offset removal. Measured performances are an overall gain variable between 21 and 47 dB, 5.6 dB noise figure, -2 dBm out-of-band IIP3, -10 dBm in-band IIP3, 44.8-dBm minimum IIP2, and -155-dBc/Hz phase noise at 135 MHz from carrier frequency, while drawing 21 mA from a 1.8-V supply. 相似文献
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An in-depth analysis of the mechanisms responsible for second-order intermodulation distortion in CMOS active downconverters is proposed in this paper. The achievable second-order input intercept point (IIP2) has a fundamental limit due to nonlinearity and mismatches in the switching stage and improves with technology scaling. Second-order intermodulation products generated by the input transconductor or due to self-mixing usually contribute to determine the IIP2 even though they can, at least in principle, be eliminated. The parasitic capacitance loading the switching-stage common source plays a key role in the intermodulation mechanisms. Moreover, the paper shows that, besides direct conversion and low intermediate frequency (IF), even superheterodyne receivers can suffer from second-order intermodulation if the IF is not carefully chosen. The test vehicle to validate the proposed analysis is a highly linear 0.18-/spl mu/m direct-conversion CMOS mixer, embedded in a fully integrated receiver, realized for Universal Mobile Telecommunications System applications. 相似文献
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F. Bonino L. Busani M. Lazzari M. Manstretta B. Rivolta B. Scrosati 《Journal of power sources》1981,6(3):261-270
A preliminary investigation of anatase, TiO2, as a positive electrode material in secondary lithium—organic electrolyte batteries is reported.Up to 0.6 lithium equivalents can react with 1 mole of TiO2. However, optimum cycling behaviour is obtained for regimes involving compositions between 0.15 and 0.45 Li/TiO2 mole ratio.Under these conditions, prolonged cycling at 0.25 – 0.5 mA cm?2 gives satisfactory results. 相似文献
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Campardo G. Micheloni R. Commodaro S. Yero E. Zammattio M. Mognoni S. Sacco A. Picca M. Manstretta A. Scotti M. Motta I. Golla C. Pierin A. Bez R. Grossi A. Modelli A. Visconti A. Khouri O. Torelli G. 《Solid-State Circuits, IEEE Journal of》2000,35(11):1655-1667
This paper presents a 3-V-only 64-Mb 4-level-cell (2-b/cell) NOR-type channel-hot-electron (CHE) programmed flash memory fabricated in 0.18-μm shallow-trench isolation CMOS technology. The device (die size 40 mm2) is organized in 64 1-Mb sectors. Hierarchical column and row decoding ensures complete isolation between different sectors during any operation, thereby increasing device reliability while still providing layout area optimization. Staircase gate-voltage programming is used to achieve narrow threshold-voltage distributions. The same program throughput as for bilevel CHE-programmed memories is obtained, thanks to parallel programming. A mixed balanced/unbalanced sensing approach allows efficient use of the available threshold window. Asynchronous (130-ns access time) and burst-mode (up to 50-MHz data rate) reading is possible. Both column and row redundancy is provided to ensure extended failure coverage. Error correction code techniques, correcting 1 failed over 32 data cells, are also integrated 相似文献
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Wireless multi-standard terminals: system analysis and design of a reconfigurable RF front-end 总被引:1,自引:0,他引:1
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Manstretta D. Laurenti N. Castello R. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2008,55(4):324-328
This paper presents an analysis on the receiver front-end architectures for multiband orthogonal frequency-division multiplexing ultra-wide-band (UWB) terminals. An interference analysis is carried out in order to derive the main linearity specifications of the receiver front-end. A reconfigurable narrow-band architecture is introduced that can best cope with the main challenges of the UWB receivers: broadband impedance matching and high out-of-band linearity. Simulation results show that linearity requirements can be achieved with sizeable margin. 相似文献
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