Bit-serial interleaved high speed division

A bit-serial/word-parallel divider circuit with simplified control requirements, is presented. The circuit uses the non-restoring division algorithm which places a restriction on the speed of the circuit. By introducing the concept of bit interleaving, a high speed design can be implemented of the same circuit complexity as an equivalent size multiplier     

Gaussian process modeling of EEG for the detection of neonatal seizures

Gaussian process (GP) probabilistic models have attractive advantages over parametric and neural network modeling approaches. They have a small number of tuneable parameters, can be trained on relatively small training sets, and provide a measure of prediction certainty. In this paper, these properties are exploited to develop two methods of highlighting the presence of neonatal seizures from electroencephalograph (EEG) signals. In the first method, the certainty of the GP model prediction is used to indicate the presence of seizures. In the second approach, the hyperparameters of the GP model are used. Tests are carried out with a feature set of ten EEG measures developed from various signal processing techniques. Features are evaluated using a neural network classifier on 51 h of real neonatal EEG. The GP measures, in particular, the prediction certainty approach, produce a high level of performance compared to other modeling methods and methods currently in clinical use for EEG analysis, indicating that they are an important and useful tool for the real-time detection of neonatal seizures.     

Testing VLSI regular arrays

In recent years the concept of Design for Test—whereby the designer is forced to comply with a specific test style—has become very popular. However, the most effective custom VLSI architectures available all have their own very strongly defined structure. Therefore, test strategies are required which exploit the typical hierarchy in the design. Exploiting this hierarchy implies a test philosophy which requires the minimum addition of extra test logic and utilizes the hierarchy of the design. A popular VLSI architecture is a systolic array which consists of a regular array of small processing elements with timing latches on the communication lines. In this case we can exploit the regularity for test purposes; in this paper we show how to do this by adopting a divide and conquor method. This can be done by generating test vectors for a single processing element, using the most appropriate fault model. The regularity of the array facilitates the propagation of these vectors to every other processing element in the array. The propagation method must also allow for the propagation of the fault effects from the output of each processing element to the boundary of the array where the fault can be observed. The proposed test method presented in this paper takes the vectors required to test a single processing element, and determines test vectors for the whole array. This method is applicable to all types of regular arrays, but in particular, systolic arrays, where we have the added problem of circuit timing. Each separate signal direction is first analyzed for its test vector and fault effect propagation properties. Then, using the array Data Dependence Graph, which represents the propagation of data through the array, the combined effect of all signals on test vector and fault effect propagation can be considered. This reduces the task of determining the array inputs to a pattern matching problem suitable for computer implementation. The test method is applied to three different arrays to illustrate how different array types can be tested.     

Instantaneous measure of EEG channel importance for improved patient-adaptive neonatal seizure detection

A measure of bipolar channel importance is proposed for EEG-based detection of neonatal seizures. The channel weights are computed based on the integrated synchrony of classifier probabilistic outputs for the channels which share a common electrode. These estimated time-varying weights are introduced within a Bayesian probabilistic framework to provide a channel specific and, thus, adaptive seizure classification scheme. Validation results on a clinical dataset of neonatal seizures confirm the utility of the proposed channel weighting for the two patient-independent seizure detectors recently developed by this research group: one based on support vector machines (SVMs) and the other on Gaussian mixture models (GMMs). By exploiting the channel weighting, the receiver operating characteristic (ROC) area can be significantly increased for the most difficult patients, with the average ROC area across 17 patients increased by 22% (relative) for the SVM and by 15% (relative) for the GMM-based detector, respectively. It is shown that the system developed here outperforms the recent published studies in this area.     

Using templates to distinguish multiplications from squaring operations

Since side channel analysis was introduced as a method to recover secret information from an otherwise secure cryptosystem, many countermeasures have been proposed to prevent leakage from secure devices. Among these countermeasures is side channel atomicity that makes operations indistinguishable using side channel analysis. In this paper, we present practical results of an attack on RSA signature generation, protected in this manner, based on the expected difference in Hamming weight between the result of a multiplication and a squaring operation. This work presents the first attack that we are aware of where template analysis can be used without requiring an open device to characterize an implementation of a given cryptographic algorithm. Moreover, an attacker does not need to know the plaintexts being operated on and, therefore, blinding and padding countermeasures applied to the plaintext do not hinder the attack in anyway.     

All-or-Nothing Transforms as a countermeasure to differential side-channel analysis

Side-channel attacks on hardware implementations of cryptographic algorithms have recently been the focus of much attention in the research community. Differential power analysis (DPA) has been shown to be particularly effective at retrieving secret information stored within an implementation. The design of DPA-resistant systems that are efficient in terms of speed and area poses a significant challenge. All-or-Nothing Transforms are cryptographic transforms, which are currently employed in numerous applications. We examine All-or-Nothing Encryption systems from the DPA perspective. This paper shows that All-or-Nothing cryptosystems, whilst not preventing side-channel leakage, do fundamentally inhibit DPA attacks. Furthermore, we develop extensions to the All-or-Nothing protocol to strengthen the DPA resistance of the cryptosystem, providing a practical alternative to masking countermeasures for symmetric ciphers.     

Algorithms and architectures for a flexible elliptic curve cryptography processor

In this paper algorithms and architectures for an new versatile type of elliptic curve cryptography processor over Galois fields GF(2 ^m ) are presented. Due to its flexibility, it readily permits changes in the system security parameters. The processor has, at its core, a novel method of performing arithmetic in GF(2 ^m ). The implementation aspects and design trade-offs of such a processor in comparison with more traditional implementations are examined through prototyping on FPGA technology.     

Optimised bit serial modular multiplier for implementation on fieldprogrammable gate arrays

A high-speed architecture for bit serial modular multiplication is presented. The design of this array is highly regular, allowing the specific logic and routing resources available in field programmable gate arrays (FPGAs) to be exploited. Furthermore, an optimised array is presented which exploits the reprogrammability of the FPGA, such that a longer bit length can be implemented on the same FPGA     

Biologic computational building blocks

Methods to represent the biological activity of oxidoreductase enzymes using logic state diagrams and to simulate the enzymes' functionings using synchronous sequential digital circuits are presented. The steps of this transform from biologics to logic involve the enzymes `electron kinetic behavior, which reveals the basic reaction pathways of the enzyme building blocks. Because these pathways are well defined, with each enzyme going through several different conformations, each conformation can be defined in terms of a logic state. The definitions can be used to describe a state machine for the enzyme building block