Multiterminal light-emitting logic device electricallyreprogrammable between OR and NAND functions

A monolithic multiterminal logic device that functions both optically and electrically as an ORNAND gate, is demonstrated for the first time. The device, based on the real-space transfer of hot electrons into a complementary collector layer, has been implemented in an InGaAs/InAlAs/InGaAs heterostructure grown by molecular beam epitaxy. Excellent performance is obtained at room temperature. The collector current and the optical output power both exhibit the OR and the NAND functions of any two of the three input terminals, these functions being interchangeable by the voltage on the third terminal     

Impact ionization and real-space transfer of minority carriers incharge injection transistors

High electric fields in the channel of InGaAs-InAlAs heterostructure complementary charge injection transistor give rise to impact ionization and real-space transfer of minority holes from the channel. These phenomena are investigated by measuring light emission in the 1.1-3.1 eV energy range for different points on the electrical characteristics. The effective carrier temperature, determined from the exponential tails of electroluminescence spectra, is 2100 K in the channel and 450 K in the barrier     

Verification of electron distributions in silicon by means of hotcarrier luminescence measurements

This paper investigates the use of hot carrier luminescence (HCL) measurements as a mean for the verification of carrier energy distribution functions in submicron silicon devices subject to high electric fields. To this purpose, physically-based two-dimensional (2-D) simulations of the spectral distribution of HCL are compared with extensive experimental data on special purpose n⁺/n/n⁺ test structures that demonstrate lateral field profiles similar to real MOSFETs without the obscuring effects of a gate electrode. Good agreement between measured and simulated data is observed over wide channel length, bias, and temperature ranges, thus providing for the first time a direct verification of simulated electron energy distributions in a MOSFET-like environment     

Compact modeling of thermal resistance in bipolar transistors onbulk and SOI substrates

Analytical expressions for the thermal resistance of bipolar transistors on bulk and SOI substrates are presented. The models are derived on the basis of intuitive physical pictures and validated by comparison with experimental data and three-dimensional (3D) device simulation. The effect of bulk and SOI substrates, shallow- and deep-trench isolation, and multiple emitter fingers is accounted for. All models are suitable for both hand calculations and computer-aided design     

BiCMOS technology for mixed-digital, analog, and RF applications

As process technology advances, we will see SoC systems with millions of digital gates combined with RF circuits operating in the tens of GHz     

Impact ionization and distribution functions in sub-micron nMOSFETtechnologies

The physics of impact ionization generated substrate current in 0.1 μm nMOSFET's technologies is clarified by comparison of experiment and full-band Monte Carlo (MC) simulation for a wide range of biases. Quasiballistic transport is confirmed. It is shown for the first time that these devices allow extraction of ionization probabilities near threshold from substrate current measurements     

Minimizing thermal resistance and collector-to-substratecapacitance in SiGe BiCMOS on SOI

We describe a low fabrication cost, high-performance implementation of SiGe BiCMOS on SOL The use of high-energy implant allows the simultaneous formation of the subcollector and an additional n-type region below the buried oxide. The combination of buried oxide layer and floating n-type region underneath results in a very low collector-to-substrate capacitance. We also show that this process option achieves a much lower thermal resistance than using SOI with deep trench isolation, both reducing cost and curbing self-heating effects     

Functional devices based on real space transfer in Si/SiGestructure

A charge injection transistor, which operates as an exclusive-OR logic gate, and a monolithic multiterminal device, electrically reprogrammable between OR and NAND logic function, have been successfully implemented in a Si-Si_0.7Ge_0.3 heterostructure grown by rapid thermal epitaxy on a Si substrate. Room temperature operation of the charge injection transistor is demonstrated, with 10 dB on/off ratio for the exclusive-OR logic function. Microwave measurements indicate a short circuit current gain cutoff of 6 GHz, for a device with a source-drain distance of 0.5 μm. Device simulations were used to identify primary dependencies of the device performance on the parameters used in the design of the structure. Further structural improvements are suggested     

Propagating avalanche position-sensitive photon detector withresolution in the micrometer and picosecond range

A position-sensitive silicon photodetector based on a new principle is introduced. The device is a special avalanche photodiode operated above the breakdown voltage. The exploited physical effect is the propagation of the avalanche perpendicularly to the electric field. The time and position (one dimension) information are extracted from the avalanche current leading edge. Experimental measurements on test structures with a position-sensitive area of 14×70 μm are presented. Spatial resolution better than 10-μm FWHM combined with ultrahigh sensitivity (single photon detection) and time resolution better than 100 ps are demonstrated     

A drift-diffusion/Monte Carlo simulation methodology for Si1-xGex HBT design

An accurate and efficient simulation methodology for Si_1-x Ge_x HBTs is presented. A two-dimensional (2-D) drift-diffusion solver is employed for dc and ac characteristics, and one-dimensional (1-D) full-band Monte Carlo for transport in the base-collector high-electric-field region. Extrinsic parasitics are introduced as lumped circuit elements whose values are obtained from measurements and layout considerations. This approach not only reduces the computational cost of the simulation, but it also helps to differentiate the relevance of the intrinsic and extrinsic device parameters. We discuss the calibration of the simulation on a 0.25 μm process and use a 1-D regional analysis in the quasi-static approximation to identify the major source of delay. Results of the delay analysis were used to improve device performance for the 0.16 μm technology node