Electrochemical process for the lamination of magnetic cores in thin-film magnetic components

The lamination of the core in thin film magnetic components is necessary to reduce the eddy current losses of the structure at high frequencies. The usual way to achieve lamination of the core is by physical vapor deposition (PVD) techniques. These methods are however costly and the deposition of layers is non selective. In this article, an almost entirely aqueous-based electrochemical process for the lamination of magnetic cores is presented. The process uses an electrodepositable photoresist Eagle 2100 ED codeposited with a catalyst (palladium). The Eagle layer is left as an insulator and the catalyst allows the activation of the layer for subsequent metallization. The process can be reproduced as many times as required for producing the multilayers. It is also selective: it does not require multiple photolithography steps. As a demonstration of the multilayer process, a core constituted of two layers of Ni/sub 80/Fe/sub 20/ (6 /spl mu/m each layer), separated by an Eagle insulating layer, electroplated over three-dimensional structures, was produced.     

Packaging and integration technologies for future high-frequency power supplies

This paper reviews data from the International Technology Roadmap for Semiconductors to establish where dc-dc converters are headed in the first decade of the new millennium. It focuses on the high performance computing (high current, fast response, high power density) and portable/handheld (low profile) sectors. Magnetics and power device packaging technologies needed to allow power supplies to move to operating frequencies in the 1-10 MHz region are discussed. It introduces the concept of magnetic components fully embedded (windings and core) in PCB and silicon offering low profile and low losses at high frequency. It also reviews developments in wirebond-free power packaging such as flip-chip assembly that offer low profile, reduced parasitics and increased thermal performance. Finally, consideration is given to the changes in the power electronics industry that may need to be addressed to enable these new technologies to play a strategic role.     

Isothermal aging effects on the microstructure and solder bump shear strength of eutectic Sn37Pb and Sn3.5Ag solders

The reliability of the eutectic Sn37Pb (63%Sn37%Pb) and Sn3.5Ag (96.5%Sn3.5%Ag) solder bumps with an under bump metallization (UBM) consisting of an electroless Ni(P) plus a thin layer of Au was evaluated following isothermal aging at 150 °C. All the solder bumps remained intact after 1500 h aging at 150 °C. Solder bump microstructure evolution and interface structure change during isothermal aging were observed and correlated with the solder bump shear strength and failure modes. Cohesive solder failure was the only failure mode for the eutectic Sn37Pb solder bump, while partial cohesive solder failure and partial Ni(P) UBM/Al metallization interfacial delamination was the main failure mode for eutectic Sn3.5Ag solder bump.     

PCB integrated inductors for low power DC/DC converter

This paper discusses the use of printed circuit board (PCB) integrated inductors for low power DC/DC buck converters. Coreless, magnetic plates and closed core structures are compared in terms of achievable inductance, power handling and efficiency in a footprint of 10 /spl times/ 10 mm/sup 2/. The magnetic layers consist of electroplated NiFe, so that the process is fully compatible with standard PCB process. Analytic and finite element method (FEM) methods are applied to predict inductor performance for typical current waveforms encountered in a buck converter. Conventional magnetic design procedures are applied to define optimum winding and core structures for typical inductor specifications. A 4.7 /spl mu/H PCB integrated inductor with dc current handling of up to 500 mA is presented. This inductor is employed in a 1.5 W buck converter using a commercial control integrated circuit (IC). The footprint of the entire converter measures 10 /spl times/ 10 mm/sup 2/ and is built on top of the integrated inductor to demonstrate the concept of integrated passives in power electronic circuits to achieve ultra flat and compact converter solutions.     

Degradation of electroless Ni(P) under-bump metallization in Sn3.5Ag and Sn37Pb solders during high-temperature storage

The interfacial reaction between electroless Ni(P) under-bump metallization (UBM) and solders is studied. A P-rich layer forms in the UBM along the solder side after reflow and thermal aging. Crack formation inside the P-rich layer can sometimes penetrate throughout the entire UBM layer structure. The Ni(P) UBM degradation occurs earlier in the Sn3.5Ag solder than in Sn37Pb because of its higher reflow temperature. Despite the formation of a P-rich layer and cracks inside the UBM, it still keeps its original function within the high-temperature storage period in this study. Explanations for the formation of the P-rich layer and cracks in the UBM are outlined along with explanations for the Ni(P) UBM degradation process.     

Magnetics on silicon: an enabling technology for power supply on chip

Data from the ITRS2003 roadmap for 2010 predicts voltages for microprocessors in hand-held electronics will decrease to 0.8V with current and power increasing to 4A and 3W, respectively. Consequently, low power converters will move to multimegahertz frequencies with a resulting reduction in capacitor and inductor values by factors of 5 and 20, respectively. Values required at 10 MHz, for a low power buck converter, are estimated at 130 nH and 0.6 uF, compatible with the integration of magnetics onto silicon and the concept of power supply-on-chip (PSOC). A review of magnetics-on-silicon shows that inductance values of 20 to 40nH/mm/sup 2/ can be achieved for winding resistances less than 1/spl Omega/. A 1-/spl mu/H inductance can be achieved at 5 MHz with dc resistance of 1/spl Omega/ and a Q of four. Thin film magnetic materials, compatible with semiconductor processing, offer power loss density that is lower than ferrite by a factor of 5 at 10 MHz. Other data reported includes, lowest dc resistance values of 120 m/spl Omega/ for an inductance of 120 nH; highest Q of 15 for an inductance of 350 nH and a current of 1 A for a 1- /spl mu/H inductor. Future technology challenges include reducing losses using high resistivity, laminated magnetic materials, and increasing current carrying capability using high aspect-ratio, electroplated copper conductors. Compatible technologies are available in the power switch, control, and packaging space. Integrated capacitor technology is still a long-term challenge with maximum reported values of 400 nF/cm/sup 2/.