Fast quadratic increase of multiport-storage-cell area with portnumber

It is shown that the space required for wordline/bitline routing leads to a quadratic multiport-storage-cell area increase with port number N, dominating from as little as N=2, N=6 for small ROM and large SRAM cell types, respectively. Larger N results in enormous area increases (e.g. by a factor of 80 for a 32-port SRAM)I making conventional multiport memories unacceptable for most practical applications     

Real structure of partially ordered crystals

Partial order in crystals is a frequently observed phenomenon in minerals and synthetic materials. The partially ordered structures are characterized by low-dimensional order of the real structure. In the case of 1D structures, the ordered units can be described as rods; 2D structures contain ordered layers. The disorder of the real structures is indicated by prominent diffuse scattering in the diffraction patterns of single crystals. No simple method for the quantitative analysis of the diffuse scattering exists, therefore the determination of essential characteristics of the structures is complicated. However, the determination can be facilitated using a combination of different methods, including electron microscopy, computation and X-ray diffraction.     

Impurity-profile-based threshold-voltage model of pocket-implanted MOSFETs for circuit simulation

A new threshold voltage (V/sub th/) model has been developed for the pocket-implant technology. The model extracts the threshold condition from the entire mobile charge concentration in the channel with only five additional parameters; the maximum doping concentration (N/sub subp/) of the pocket profile, the penetration length (L/sub p/) into the channel, and three enhanced short-channel parameters. The model reproduces the measured V/sub th/ versus. gate-length (L/sub gate/) characteristics with an average error of a few millivolts under any bias conditions.     

Distributed crossbar architecture for area-efficient combined data/instruction caches with multiple ports

A proposal to improve the low access bandwidth of conventional one-port caches by utilising a multi-bank structure with distributed crossbar to increase port number at small additional area cost is presented. This enables combination of data and instruction caches into a single multi-port cache as well as different wordlength for each port. Through dynamically scheduling the storage space used for data and instructions, 25% smaller storage capacity is sufficient for a given maximum cache-miss probability.     

A Gate‐Current Model for Advanced MOSFET Technologies Implemented into HiSIM2

A gate leakage current model for advanced MOSFETs has been developed and implemented into the Hiroshima‐university STARC IGFET Model (HiSIM), the first complete surface‐potential‐based model. The model consists of four tunneling mechanisms, the gate to channel/bulk/source/drain, and requires totally 15 model parameters covering all bias conditions. Simulation results reproduce measurement for any device size and temperature without binning. Validity of the model has been tested with circuits that are sensitive to the change of stored charge due to tunneling current. Copyright © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Piecewise‐planar Reconstruction of Multi‐room Interiors with Arbitrary Wall Arrangements

Reconstructing the as‐built architectural shape of building interiors has emerged in recent years as an important and challenging research problem. An effective approach must be able to faithfully capture the architectural structures and separate permanent components from clutter (e.g. furniture), while at the same time dealing with defects in the input data. For many applications, higher‐level information on the environment is also required, in particular the shape of individual rooms. To solve this ill‐posed problem, state‐of‐the‐art methods assume constrained input environments with a 2.5D or, more restrictively, a Manhattan‐world structure, which significantly restricts their applicability in real‐world settings. We present a novel pipeline that allows to reconstruct general 3D interior architectures, significantly increasing the range of real‐world architectures that can be reconstructed and labeled by any interior reconstruction method to date. Our method finds candidate permanent components by reasoning on a graph‐based scene representation, then uses them to build a 3D linear cell complex that is partitioned into separate rooms through a multi‐label energy minimization formulation. We demonstrate the effectiveness of our method by applying it to a variety of real‐world and synthetic datasets and by comparing it to more specialized state‐of‐the‐art approaches.     

Distributed against centralised crossbar function for realising bank-based multiport memories

The two extreme functionally equivalent possibilities of distributed or centralised crossbar function for realising a bank-based multiport memory are compared on the basis of required global signal and transistor numbers. With respect to both measures, the distributed crossbar function is found to be the better choice for practically relevant multiport-memory configurations.     

Compact associative-memory architecture with fully parallel searchcapability for the minimum Hamming distance

An associative-memory architecture for a fully parallel minimum Hamming distance search is proposed, which uses digital circuitry for bit comparison and fast analog circuitry for word comparison as well as winner-take-all (WTA) functionality. Following this original approach allows compact and high-performance integration in conventional CMOS technology. First, static encoding of word-comparison results as a current-sink capability reduces word-comparison circuitry to the theoretical minimum, namely, one transistor per bit and one signal line per word. Second, a new WTA principle, which we call self-adapting winner line-up amplification (WLA), regulates the winner row output automatically into the narrow maximum-gain region of a distance amplifier. Third, winner search circuit complexity scales linear with reference-word number and not quadratic as inevitable for digital approaches. Due to static distance encoding and WLA regulation, transient noise and fabrication process variations are largely tolerated. Only relative chip-internal transistor-parameter variations, creating effective mismatch of matched transistors, limit winner search result correctness. Practical feasibility is verified     

Temporal Coherence Methods in Real‐Time Rendering

Nowadays, there is a strong trend towards rendering to higher‐resolution displays and at high frame rates. This development aims at delivering more detail and better accuracy, but it also comes at a significant cost. Although graphics cards continue to evolve with an ever‐increasing amount of computational power, the speed gain is easily counteracted by increasingly complex and sophisticated shading computations. For real‐time applications, the direct consequence is that image resolution and temporal resolution are often the first candidates to bow to the performance constraints (e.g. although full HD is possible, PS3 and XBox often render at lower resolutions). In order to achieve high‐quality rendering at a lower cost, one can exploit temporal coherence (TC). The underlying observation is that a higher resolution and frame rate do not necessarily imply a much higher workload, but a larger amount of redundancy and a higher potential for amortizing rendering over several frames. In this survey, we investigate methods that make use of this principle and provide practical and theoretical advice on how to exploit TC for performance optimization. These methods not only allow incorporating more computationally intensive shading effects into many existing applications, but also offer exciting opportunities for extending high‐end graphics applications to lower‐spec consumer‐level hardware. To this end, we first introduce the notion and main concepts of TC, including an overview of historical methods. We then describe a general approach, image‐space reprojection, with several implementation algorithms that facilitate reusing shading information across adjacent frames. We also discuss data‐reuse quality and performance related to reprojection techniques. Finally, in the second half of this survey, we demonstrate various applications that exploit TC in real‐time rendering.