A 24-channel implantable neural recording based on time and frequency-division multiplexing

This paper presents a novel approach to encapsulate prerecorded neural signals in implantable neural recording microsystems. We have increased the number of channels and the reconstructed neural signal quality in the receiver by combining time-division-multiplexing (TDM) and frequency-division-multiplexing (FDM) method. Reducing the number of channels in each TDM module is the fundamental advantage of this method that leads to reduced crosstalk noise. We evaluate some possible configurations and propose an optimized system that has less power dissipation and area occupation than other configurations. A 24-channel implantable neural recording based on the optimized system is designed in both system and circuit level. In this system, first, channels are divided into three 8-channel groups then after multiplexing in the time domain, they are combined together by FDM method. Finally, a frequency modulator wirelessly transmits neural signals to an external setup. In addition, we adjust local carrier frequencies and the bandwidth of TDM to synchronize detection without transmitting pilot carrier. To justify the system operation, using 0.18 μm CMOS technology, we design the system in circuit level. The designed circuit consumes a power of 1.39 mW at a supply voltage of 1.8 V. This leads to a power consumption of 58 μW per channel.     

1-bit quantiser with rail to rail input range for sub-1 V /spl Delta//spl Sigma/ modulators

A new, fully differential comparator with rail to rail input range is presented. This comparator can be used as a 1-bit quantiser in sub-1 V /spl Delta//spl Sigma/ modulators. The quantiser is laid out in 0.18 /spl mu/m CMOS technology. The post-layout simulation results show that the quantiser is capable of working at 10 MHz with 10 /spl mu/V resolution. This quantiser is successfully used in 0.8 V first-order and second-order fully differential /spl Delta//spl Sigma/ modulators.     

A new non-uniform adaptive-sampling successive approximation ADC for biomedical sparse signals

This paper presents a new sampling technique and a successive approximation analog to digital converter (SA-ADC) which samples sparse signals in a non-uniform adaptive way. The proposed sampling technique has the capability to be incorporated in the structure of the SA-ADC. The proposed SA-ADC changes the rate of sampling in accordance with the rate of changes of the signal. In this way, the data volume is reduced considerably without losing the important information in the signal. Simulation results in the 0.18 um CMOS technology shows a power saving of up to 90.5 % and a compression ratio of 7.5 compared to the conventional sampling technique of ECG signals.     

A novel data transfer technique for bio-implantable devices through the inductive power transfer link

A novel technique for transferring data to biomedical implantable devices through the inductive power transfer link is presented. The new modulation technique presented in this paper is based on changing the duty cycle of the switching pulse of the class E power amplifier which drives the external coil. Hence, we call it duty cycle shift keying (DCSK). Inductive link efficiency and voltage gain are analyzed for the DCSK technique. Based on the mathematical analysis of the proposed technique its bit error rate is close to that of the BFSK. However, it can achieve a data rate to carrier frequency of 100 %. The modulator and demodulator of the proposed technique are simple and make it suitable for bio-implantable devices. The proposed circuit is simulated by advanced design system simulator using the 0.18 μm CMOS technology. Moreover, in order to verify the effectiveness of the proposed technique, a test setup is implemented using off-the-shelf components. The simulation as well as measurement results will be provided in this article.     

Low-voltage low-power Gm-C filters: a modified configuration for improving performance

In this paper, after addressing the effect of finite output impedance of Gm cells on the performance of Gm-C filters, a modified configuration suitable for low-voltage operation is presented. In the proposed architecture, to efficiently increase the output impedance, body-driven impedance boosting is employed. The circuit-level topology of Gm cells is modified in order to increase the output impedance with minimized power consumption. To show the effectiveness of the proposed scheme, a 0.9-V 5-th order Butterworth low-pass filter with 8 MHz cutoff frequency is designed and simulated in 90-nm CMOS technology. Employing the proposed technique, power consumption is reduced from 0.7 mW to 0.5 mW.     

A bridge technique for memristor state programming

ABSTRACT

In order to effectively use a memristor in analog circuits, its memristance should be adjusted to a desired value between its limits. Since the maximum and minimum required memristance typically varies considerably between different types of memristors, it is almost impossible to tune the resistance of each memristor based on a reference resistor. Which is mostly done using some programmer circuits. Moreover, those programming strategies involving pulses are time-consuming and they impose high hardware headroom. In this paper, a novel CMOS circuit is presented for programming memristors. A Wheatstone bridge circuit is used to measure the current memristance, while the programming current is flowing through the device. Using such an approach reading the state and its adjustment are done simultaneously, which reduces the programming latency. In the proposed method, instead of tuning the memristance, the state of the memristor will be set to the desired value, which is proportional to a control voltage. The low programming latency, six-bit accuracy, and use of a simple circuit for programming, are the main advantages of our solution. The proposed circuit is designed and laid out in 0.35 µm CMOS technology and takes 0.0273mm². Furthermore, the proposed approach is applied to a memristor emulator to demonstrate its correct operation in real applications.     

Continuous time common mode feedback technique for sub 1 V analogue circuits

A continuous time common mode feedback technique for sub 1 V analogue circuits using the bulk PMOS dynamic threshold (BP-DTMOS) technique is presented. The proposed method is used in a 0.8 V folded cascode amplifier in 0.18 /spl mu/m CMOS technology. The schematic and the post-layout simulation results show that this technique is effective in reducing common mode errors caused by process or environmental variations. It also improves the CMRR of the amplifier.     

A monotonic digitally controlled delay element

A monotonic digitally controlled delay element (DCDE) is implemented in the 0.18 /spl mu/m CMOS technology. In this paper, the design procedure of the new architecture and measurement results are reported. The delay of the DCDE changes monotonically with respect to the digital input vector. The monotonicity is one of the important features of this new architecture. Due to its monotonic behavior, the design of the DCDE is rather straightforward. The DCDE can be analyzed by a simple set of empirical equations with reasonable accuracy and can be made more tolerant to process, temperature, and supply voltage variations. The implemented delay element provides a delay resolution of as low as 2 ps and consumes 170 /spl mu/W to 340 /spl mu/W static power depending on the digital input vector.     

A digitally programmable delay element: design and analysis

Variable delay elements are often used to manipulate the rising or falling edges of the clock or any other signal in integrated circuits (ICs). Delay elements are also used in delay locked loops (DLLs). Although, a few types of digitally controlled delay elements have been proposed, an analytical expression for the delay of these circuits has not been reported. In this paper, we propose a new delay element architecture and develop an analytical equation for the output voltage and an empirical relation for the delay of the circuit. The proposed circuit exhibits improved delay characteristics over previously reported digitally controlled delay elements.