Generation of Technology-Independent Retargetable Analog Blocks

This paper introduces a complete methodology for retargeting of analog cells to different sets of specifications. This methodology is technology-independent, thus allowing the migration, from one technology to another, of the circuit under retargeting. Careful integration of the device sizing and layout generation tasks via the incorporation of layout constraints during the sizing process allows to generate fully functional designs in a few minutes. The methodology is illustrated via the retargeting of a fully-differential Miller-compensated two-stage operational amplifier for a new set of specifications and two different technological processes.An erratum to this article can be found at     

A vertically integrated tool for automated design of /spl Sigma//spl Delta/ modulators

We present a tool that starting from high-level specifications of switched-capacitor (SC) /spl Sigma//spl Delta/ modulators calculates optimum specifications for their building blocks and then optimum sizes for the block schematics. At both design levels, optimization is performed using statistical techniques to enable global design and innovative heuristics for increased computer efficiency as compared with conventional statistical optimization. The tool uses an equation-based approach at the modulator level, a simulation-based approach at the cell level, and incorporates an advanced /spl Sigma//spl Delta/ behavioral simulator for monitoring and design space exploration. We include measurements taken from two silicon prototypes: (1) a 16 b @ 16 kHz output rate second-order /spl Sigma//spl Delta/ modulator; and (2) a 17 b @ 40 kHz output rate fourth-order /spl Sigma//spl Delta/ modulator. Both use SC fully differential circuits and were designed using the proposed tool and manufactured in a 1.2 /spl mu/m CMOS double-metal double-poly technology.<>     

High resolution CMOS current comparators: design and applications to current-mode function generation

This paper uses fundamental models to derive design conditions for maximum speed and resolution in CMOS transimpedance comparators. We distinguish two basic comparator architectures depending on whether the input sensing node is resistive or capacitive, and show that each type yields advantages for different ranges of input current. Then, we introduce a class of current comparator structures which use nonlinear sensing and/or feedback to combine the advantages of capacitive-input and resistive-input architectures. Two members of this class are presented demonstrating resolution levels (measured on silicon prototypes) in the range of pAs. They exhibit complementary functional features: one, the current steering comparator, displays better transient response in the very comparison function, while operation of the other, the current switch comparator, is easily extended to support systematic generation of nonlinear transfer functions in current domain. The paper explores also this latter extension, and presents current-mode circuit blocks for systematic generation of nonlinear functions based on piecewise-linear (PWL) approximation. Proposals made in the paper are demonstrated via CMOS prototypes in two single-poly CMOS n-well technologies: 2m and 1.6m. These prototypes show measured input current comparison range of 140 dB, resolution and offset below 10 pA, and operation speed two orders of magnitude better than that of conventional resistive-input circuits. Also, measurements from the PWL prototypes show excellent rectification properties (down to a few pAs) and small linearity errors (down to 0.13%).     

Highly linear 2.5-V CMOS /spl Sigma//spl Delta/ modulator for ADSL+

We present a 90-dB spurious-free dynamic range sigma-delta modulator (/spl Sigma//spl Delta/M) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-/spl mu/m CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within /spl plusmn/0.85 and /spl plusmn/0.80 LSB/sub 14 b/, respectively. The /spl Sigma//spl Delta/ modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the /spl Sigma//spl Delta/ modulator.     

Architectures and design considerations for wireline ΣΔ modulators beyond ADSL

In this paper we discuss design considerations for sigma–delta modulators (ΣΔMs) aimed at high-linearity high-speed A/D conversion, as required in emerging wireline access applications. In order to achieve resolutions in the range of 12–15 bit with sufficiently low oversampling ratio, we analyze the performance of a family of high-order cascade architectures in a low-voltage deep-submicron scenario. We show that, after proper architecture selection, guided by a simple power estimation method, these ΣΔMs are good candidates to achieve ADSL performances in coming CMOS processes. Experimental results on a prototype for ADSL+ applications designed in 2.5-V 0.25-μm CMOS suggest the possibility of programming or reusing the design for other telecom applications, thanks to the easiness to expand or shrink this family of cascade ΣΔMs to other orders. Estimated performance of the adapted prototype for ISDN, SDSL, and VDSL applications provides promising results.     

High-level synthesis of switched-capacitor, switched-current and continuous-time /spl Sigma//spl Delta/ modulators using SIMULINK-based time-domain behavioral models

This paper presents a high-level synthesis tool for /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/Ms) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for the modulator implementation are considered: switched-capacitor, switched-current and continuous-time. The behavioral models of these circuits, that take into account the most critical limiting factors, have been incorporated into the SIMULINK environment by using S-function blocks, which drastically increase the computational efficiency. The precision of these models has been validated by electrical simulations using HSPICE and experimental measurements from several silicon prototypes. The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for /spl Sigma//spl Delta/M synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, processing capabilities, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of /spl Sigma//spl Delta/Ms using both discrete-time and continuous-time circuit techniques.     

Reliable analysis of settling errors in SC integrators: applicationto ΣΔ modulators

A study is presented into the transient response of SC integrators considering amplifier finite bandwidth, slew-rate, and parasitic capacitors during, unlike previous models, both the integration and sampling phases. The model is validated by experimental results on a second-order ΣΔ modulator and provides more reliable estimations of the defective settling in high-speed designs than previously reported models     

A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulatorin CMOS 0.7-μm single-poly technology

This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators-referred to as a 2-1-1_mb architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2.1.1_single-bit modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four     

CMOS fully-differential bandpass ΣΔ modulator usingswitched-current circuits

The authors present a fourth-order bandpass ΣΔ switched-current modulator IC in 0.8 μm CMOS single-poly technology. It is the first reported integrated circuit realisation of a bandpass ΣΔ modulator using switched-current circuits. Its architecture is obtained by applying a lowpass to bandpass transformation (z¹→-z²) to a second-order lowpass modulator. It has been realised using fully-differential circuitry with common-mode feedback. Measurements show 8 bit dynamic range up to 5 MHz clock frequency     

Analysis of Error Mechanisms in Switched-Current Sigma-Delta Modulators

This paper presents a systematic analysis of the major switched-current (SI) errors and their influence on the performance degradation of ΣΔ Modulators (ΣΔMs). The study is presented in a hierarchical systematic way. First, the physical mechanisms behind SI errors are explained and a precise modeling of the memory cell is derived. Based on this modeling, the analysis is extended to other circuits of higher level in the modulator hierarchy such as integrators and resonators. After that, the study is extended to the modulator level, considering two fundamental architectures: a 2nd-order LowPass ΣΔM (2nd-LPΣΔM) and a 4th-order BandPass ΣΔM (4th-BPΣΔM). The noise shaping degradation caused by the linear part of SI errors is studied in the first part of the paper. This study classifies SI non-idealities in different categories depending on how they modify the zeroes of the quantization noise transfer function. As a result, closed-form expressions are found for the degradation of the signal-to-noise ratio and for the change of the notchfrequency position in the case of 4th-BPΣΔMs. The analysis is treated considering both the isolated and the cumulative effect of errors. In the second part of the paper the impact of non-linear errors on the modulator performance is investigated. Closed-form expressions are derived for the third-order harmonic distortion and the third-order intermodulation distortion at the output of the modulator as a function of the different error mechanisms. In addition to the mentioned effects, thermal noise is also considered. The most significant noise sources of SI ΣΔMs are identified and their contributions to the input equivalent noise are calculated. All these analyses have been validated by SPICE electrical simulations at the memory cell level and by time-domain behavioural simulations at the modulator level. As an experimental illustration, measurements taken from a 0.8 μm CMOS SI 4th-BPΣΔM silicon prototype validate our approach.