排序方式: 共有14条查询结果,搜索用时 15 毫秒
1.
Meghelli M. Rylyakov A.V. Zier S.J. Sorna M. Friedman D. 《Solid-State Circuits, IEEE Journal of》2003,38(12):2147-2154
A 43-Gb/s receiver (Rx) and transmitter (Tx) chip set for SONET OC-768 transmission systems is reported. Both ICs are implemented in a 0.18-/spl mu/m SiGe BiCMOS technology featuring 120-GHz f/sub T/ and 100 GHz f/sub max/. The Rx includes a limiting amplifier, a half-rate clock and data recovery unit, a 1:4 demultiplexer, a frequency acquisition aid, and a frequency lock detector. Input sensitivity for a bit-error rate less than 10/sup -9/ is 40 mV and jitter generation better than 230 fs rms. The IC dissipates 2.4 W from a -3.6-V supply voltage. The Tx integrates a half-rate clock multiplier unit with a 4:1 multiplexer. Measured clock jitter generation is better than 170 fs rms. The IC consumes 2.3 W from a -3.6-V supply voltage. 相似文献
2.
Lei Shan Meghelli M. Joong-Ho Kim Trewhella J.M. Oprysko M.M. 《Advanced Packaging, IEEE Transactions on》2002,25(2):248-254
A 50 Gb/s package for SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer targeting SONET OC-768 serial communication systems is introduced in this work. The package was designed to facilitate bit-error-rate tests and constructed with high-speed coaxial connectors, transmission lines on ceramic substrate, ribbon bonds for chip-to-package interconnects, and a metal composite housing. Numerical simulations were conducted to guide the package design, and both small signal measurements and operational tests were performed thereafter to verify the design and modeling concepts. To keep the model structure under the existing computing capability, the simulation was segmented into three sections - coaxial connector to transmission line, transmission line alone, and transmission line to ribbon bond, and then the results were assembled to predict the performance of the entire package. The package was operated up to 50 Gb/s with low degradation to input digital waveforms and free of error. 相似文献
3.
A driver IC and a 2:1 selector-driver IC developed for lightwave modulators are presented. The IC's were fabricated in a standard InP/InGaAs double heterojunction bipolar transistor technology with 56 GHz Ft and 43 GHz Fmax. The driver operates up to 20 Gb/s with an output voltage swing of 4 Vpp (corresponding to an internal current swing of 120 mA). The 2:1 selector-driver exhibits an output voltage swing of 2.2 Vpp at 30 Gb/s. Specific design and layout aspects of such circuits are discussed 相似文献
4.
Jagannathan B. Meghelli M. Rylyakov A.V. Groves R.A. Chinthakindi A.K. Schnabel C.M. Ahlgren D.A. Freeman G.G. Stein K.J. Subbanna S. 《Electron Device Letters, IEEE》2002,23(9):541-543
This letter reports on the room temperature operation of a conventional SiGe bipolar ECL ring oscillator with a minimum stage delay of 4.2 ps for ~250 mV single ended voltage swing. To our knowledge, this is the lowest reported delay for a gate fabricated using transistor devices. The circuit uses 0.12 × 2 μm2 emitter size SiGe n-p-n transistors with a room temperature fT of 207 GHz and fMAX (unilateral gain extrapolation) of 285 GHz. The ring oscillator was studied as a function of various device and circuit parameters and it was found that minimum delay is more dependent on the parasitic resistance and capacitance in the n-p-n device than on pure transit time across the device 相似文献
5.
A 43-Gb/s full-rate clock transmitter chip for SONET OC-768 transmission systems is reported. The IC is implemented in a 0.18-/spl mu/m SiGe BiCMOS technology featuring 120 GHz f/sub T/ and 100 GHz f/sub max/ HBTs. It consists of a 4:1 multiplexer, a clock multiplier unit, and a frequency lock detector. The IC features clock jitter generation of 260 fs rms and dissipates 2.3 W from a -3.6-V supply voltage. Measurement results are compared to a previously reported half-rate clock transmitter designed using the same technology. 相似文献
6.
This article presents a new storage-retrieval method called In-Deep Class Storage, designed for Flow-Rack AS/RS. Class-based storage is a well-known method that has an extensive literature; our method is based on the fact that it is more efficient to dedicate the front layers of each bin to the class of the most popular items rather than dedicating whole bins close to the drop-off station. Clearly, this idea is not trivial to implement due to the dynamic behaviour of such racks. Thus, two separate algorithms have been defined, one for storage and one for retrieval, enabling dynamic use of our approach, with the only hypothesis of a Pareto distribution of item demand. This article presents a simulation study designed to compare the performance of random storage and retrieval with the use of the algorithms. This study shows a significant improvement of the expected retrieval delay, the main performance indicator selected for the study. 相似文献
7.
4:1 multiplexer and 1:4 demultiplexer ICs targeting SONET OC-768 applications are reported. The ICs have been implemented using a 120-GHz-f/sub T/ 0.18-/spl mu/m SiGe BiCMOS process. Both ICs have been packaged to enable bit error rate testing by connecting their serial interfaces. Error-free operation has been achieved for both circuits at data rates beyond 50 Gb/s. At a -3.6-V supply voltage, the multiplexer and demultiplexer dissipate 410 and 430 mA, respectively. Switching behavior of the 4:1 multiplexer has also been checked up to 70 Gb/s. 相似文献
8.
Buckwalter J.F. Meghelli M. Friedman D.J. Hajimiri A. 《Solid-State Circuits, IEEE Journal of》2006,41(6):1391-1399
A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase pre-emphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6Gb/s and 600mVpp output swing, a power budget of 3mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24mW, a budget of 4 mW/Gb/s. 相似文献
9.
Freeman G. Meghelli M. Kwark Y. Zier S. Rylyakov A. Sorna M.A. Tanji T. Schreiber O.M. Walter K. Jae-Sung Rieh Jagannathan B. Joseph A. Subbanna S. 《Solid-State Circuits, IEEE Journal of》2002,37(9):1106-1114
Product designs for 40-Gb/s applications fabricated from SiGe BiCMOS technologies are now becoming available. In this paper we first briefly discuss heterojunction bipolar transistor (HBT) device operation at high speed, demonstrating that perceived concerns regarding lower BV/sub CEO/ and higher current densities required to operate silicon HBTs at such high speeds do not in actuality limit design or performance. The high-speed portions of the 40-Gb/s system are then addressed individually. We demonstrate the digital capability through a 4: 1 multiplexer and a 1 : 4 demultiplexer running over 50 Gb/s error free at a -3.3-V power supply. We also demonstrate a range of analog elements, including a lumped limiting amplifier which operates with a 35-GHz bandwidth, a transimpedance amplifier with 220-/spl Omega/ gain and 49.1-GHz bandwidth, a 21.5-GHz voltage-controlled oscillator with over -100-dBc/Hz phase noise at 1-MHz offset, and a modulator driver which runs a voltage swing twice the BV/sub CEO/ of the high-speed SiGe HBT. These parts demonstrate substantial results toward product offerings, on each of the critical high-speed elements of the 40-Gb/s system. 相似文献
10.
SiGe heterojunction bipolar transistors and circuits toward terahertz communication applications 总被引:4,自引:0,他引:4
Jae-Sung Rieh Jagannathan B. Greenberg D.R. Meghelli M. Rylyakov A. Guarin F. Zhijian Yang Ahlgren D.C. Freeman G. Cottrell P. Harame D. 《Microwave Theory and Techniques》2004,52(10):2390-2408
The relatively less exploited terahertz band possesses great potential for a variety of important applications, including communication applications that would benefit from the enormous bandwidth within the terahertz spectrum. This paper overviews an approach toward terahertz applications based on SiGe heterojunction bipolar transistor (HBT) technology, focusing on broad-band communication applications. The design, characteristics, and reliability of SiGe HBTs exhibiting record f/sub T/ of 375 GHz and associated f/sub max/ of 210 GHz are presented. The impact of device optimization on noise characteristics is described for both low-frequency and broad-band noise. Circuit implementations of SiGe technologies are demonstrated with selected circuit blocks for broad-band communication systems, including a 3.9-ps emitter coupled logic ring oscillator, a 100-GHz frequency divider, 40-GHz voltage-controlled oscillator, and a 70-Gb/s 4:1 multiplexer. With no visible limitation for further enhancement of device speed at hand, the march toward terahertz band with Si-based technology will continue for the foreseeable future. 相似文献