Simultaneous switching noise reduction by resonant clock distribution networks

Resonant clock distribution networks are known as low-power alternatives for conventional power-hungry buffer-driven clock networks. In this paper, we investigate the simultaneous switching noise (SSN) in a resonant clock network compared to that in conventional clocking. Analytical and simulation results show that employing the clock generated by a resonant clock network reduces the SSN voltage on power supply rails. The main drawback of using a sinusoidal clock is that the short-circuit power increases in the clocked devices. This problem is also investigated and discussed analytically.     

Effects of functional electrical stimulation on the joints of adolescents with spinal cord injury

Nineteen adolescent subjects with complete spinal cord injuries resulting in paraplegia or tetraplegia participated in a functional electrical stimulation (FES) program consisting of computerized, controlled exercise and/or weight bearing. The effects of stimulated exercise and standing/walking on the lower extremity joints were prospectively studied. Plain radiographs and MRIs were obtained prior to and following completion of the exercise and standing and walking stages. In addition, the joints of five subjects were studied with synovial biopsies, arthroscopy, and the analysis of serum and synovial fluid for a 550 000 dalton cartilage matrix glycoprotein (CMGP). Pre-exercise joint abnormalities secondary to the spinal cord injury improved following the stimulation program. None of the subjects developed Charcot joint changes. Upon standing with FES, one subject with poor hip coverage prior to participation developed hip subluxation which required surgical repair. No other detrimental clinical effects occurred in the lower extremity joints of subjects participating in an FES program over a 1-year period.     

Correction to: Surface‐Active Properties of Solvent‐Extracted Panax ginseng Saponin‐Based Surfactants

In the original version of the paper, the corresponding author was listed as Iraj Mesgarzadeh. At the request of the authors, the corresponding author changed to Rahmatollah Rahimi. Dr. Rahimi can be contacted at rahimi_rah@iust.ac.ir.     

Jitter Characteristic in Charge Recovery Resonant Clock Distribution

This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by considering the data-dependent nature of the generated jitter, the reason for the undesired jitter-peaking phenomenon is investigated. The analysis has been verified by measurements on a test chip fabricated in 0.13-mum standard CMOS process. The chip includes a fully integrated 1.5-GHz LC clock resonator with a passive (bufferless) clock distribution network, which directly drives the clocked devices in pipelined data path circuits. Furthermore, a jitter suppression technique based on injection locking is presented. Measurement results show about 50% peak-to-peak clock jitter reduction from 28.4 ps down to 14.5 ps after injection locking.