Circuit sensitivity to interconnect variation

Deep submicron technology makes interconnect one of the main factors determining the circuit performance. Previous work shows that interconnect parameters exhibit a significant amount of spatial variation. In this work, we develop approaches to study the influence of the interconnect variation on circuit performance and to evaluate the circuit sensitivity to interconnect parameters. First, an accurate interconnect modeling technique is presented, and an interconnect model library is developed. Then, we explore an approach using parameterized interconnect models to study circuit sensitivity via a ring oscillator circuit. Finally, we present an alternative approach using statistical experimental design techniques to study the sensitivity of a large and complicated circuit to interconnect variations     

Modeling of the breakdown mechanisms for porous copper/low-k process flows

The lifetime of porous low-k dielectrics has been observed to degrade as a function of porosity. This paper demonstrates that pores disturb the electric field within a dielectric through finite element simulation. The disturbance of electric field extends beyond the pore itself. A model of charge transport has been developed to demonstrate the sensitivity of leakage currents in a dielectric to porosity.     

Analysis of the impact of proximity correction algorithms oncircuit performance

Variation in channel length degrades circuit reliability and yield. A common way to compensate for this problem is to increase the mean channel length, which, unfortunately, degrades circuit performance for digital circuits. One source of channel length variation is lithography, during which the line width is influenced by local layout patterns. It is possible to compensate for this effect by resizing transistor gates appropriately on the mask. However, the effectiveness of the correction is limited by constraints such as the mask correction resolution. To determine how to design a good correction scheme with limited resources, we have developed a method to compare different correction algorithms in terms of their impact on the performance of one of the main functional blocks in a state-of-the-art microprocessor. In particular, to evaluate correction algorithms while avoiding the high cost associated with generating multiple mask sets and fabricating product wafers with each of these mask sets, we present a method for predicting the correction results using simulation. Our methodology involves a DRC-based approach for gate resizing, along with critical path simulation for evaluating circuit performance. In-line CD measurement data were used to measure the impact of the proximity effect on transistor channel length. Electrical test results were used to calibrate the device models for circuit simulation     

The application of submicron lithography defect simulation to ICyield improvement

Yield improvement efforts traditionally involve extensive experimental work aimed at diagnosis of defect sources. This paper proposes a methodology for supplementing such experimental work with defect simulation. In particular, it is shown that lithography defect simulation can provide insight into defect mechanisms that cause major distortions in photoresist profiles. The nature of the distorted patterns can assist us in yield improvement efforts, since by comparing simulation results with the observed photoresist profiles on wafers, defect sources may be identified. Several lithography defect diagnosis examples are presented to demonstrate the approach     

Yield modeling based on in-line scanner defect sizing and acircuit's critical area

Wafers containing a large number of defects on any layer should be discarded in order to avoid the cost associated with processing wafers that are unlikely to yield. Normally decisions about scrapping wafers are based on defect counts. However, including the size of defects can improve the accuracy of such dispositions. If the size of defects is taken into account, critical area provides an estimate of the kill ratio associated with defects of a given size, where the critical area of a layer of a circuit is computed from a circuit's layout. In this paper, the accuracy of the sizing of defects by in-line scanners is analyzed. Then, the impact of defect sizing inaccuracy on estimates of layer yield is discussed, and a methodology to more accurately compute layer yield and kill ratios is presented, which calibrates for inaccuracy in defect sizing by in-line scanners     

Study of Area Scaling Effect on Integrated Circuit Reliability Based on Yield Models

Two models for the effect of area scaling on reliability are derived from two distinct yield models with different assumptions on defect distributions. One is derived from the Poisson yield model assuming a uniform random distribution of defects as in an early model. The other is based on the negative binomial yield model to account for deviation from a uniform random distribution of defects caused by clustering. Experimental data from backend test structures show that the model based on defect clustering explains observed data well while the model assuming a uniform random distribution shows a significant departure from it.     

Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level correction

The authors present a comprehensive characterization method applied to the study of the state-of-the-art 18-/spl mu/m CMOS process. Statistical characterization of gate CD reveals a large spatial intrafield component, strongly dependent on the local layout patterns. The authors describe the statistical analysis of this data and demonstrate the need for such comprehensive characterization. They describe the experimental setup of the novel measurement-based characterization approach that is capable of capturing all the relevant CD variation patterns necessary for accurate circuit modeling and statistical design for increased performance and yield. Characterization is based upon an inexpensive electrically based measurement technique. A rigorous statistical analysis of the impact of intrafield variability on circuit performance is undertaken. They show that intrafield CD variation has a significant detrimental effect on the overall circuit performance that may be as high as 25%. Moreover, they demonstrate that the spatial component of gate CD variability, rather than the proximity-dependent component, is predominantly responsible for speed degradation. In order to reduce the degradation of circuit performance and yield, the authors propose a mask-level spatial gate CD correction algorithm to reduce the intrafield and overall variability and provide an analytical model to evaluate the effectiveness of correction for variance reduction. They believe that potentially significant benefits can be achieved through implementation of this compensation technique in the production environment.     

Ultrastructural PMP22 expression in inherited demyelinating neuropathies

The purpose of this study was to determine the accuracy of a video system which our laboratory has been using to measure soft tissue strain. Both static and dynamic error analyses were performed to assess the accuracy of our video system. Static error was defined as the amount of movement reported by the video system for markers that were stationary. Dynamic error was defined as the difference between the motion of the markers as reported by the video system and their actual motion. Two sets of fluorescent markers were attached to a servo-hydraulic materials test machine. One marker set was attached to the hydraulic actuator (moving markers) and the other set was attached to the base of the machine (stationary markers). Five different marker sizes, five camera distances, and seven different loading rates were studied. Results indicated that the static error was independent of marker size, and that the dynamic error was independent of the loading rate and marker size for loading rates of 50% of the camera field of view (CFV) per second or slower. For loading rates greater than 50 percent of CFV per second, the marker size did have an affect on the dynamic error. The mean static error was found to be 0.026 percent of CFV and the mean dynamic error was found to be 0.062 percent of CFV.     

Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown

Low-k time-dependent dielectric breakdown (TDDB) has been found to be a function of metal linewidth, when the distance between the lines is constant. Modeling requires determining the relationship between TDDB and layout geometries. To determine this relationship, comb test structures have been design and implemented in 45 nm technology. In this work, low-k dielectric breakdown, low-k dielectric vulnerable areas, and linewidth variation are linked to full chip lifetimes.     

A methodology to extract failure rates for low-k dielectric breakdown with multiple geometries and in the presence of die-to-die linewidth variation

Backend geometries on chips contain a wide variety of features. This paper analyzes data from test structures implemented on a 45 nm technology test chip to relate geometry to failure rate statistics. An area scaling model is constructed which accounts for the presence of die-to-die linewidth variation, and a methodology is proposed to account for die-to-die linewidth variation when determining if low-k materials satisfy lifetime requirements.