A power-driven multiplication instruction-set design method for ASIPs

This paper presents a novel power-driven multiplication instruction-set design method for application-specific instruction-set processors (ASIPs). Based on a dual-and-configurable-multiplier structure, our proposed method devises a multiplication instruction set for low-power ASIPs. Our method exploits the execution sequences of multiplication instructions and effective bit widths of variables to reduce power consumed by redundant multiplication bits while minimizing the multiplication execution time. Experimental results on a set of DSP programs demonstrate that our proposed method achieves significant power reduction (up to 18.53%) and execution time improvement (up to 10.43%) with 18% area overhead.     

Microstrip stepped impedance resonator bandpass filter with an extended optimal rejection bandwidth

Bandpass filters with an optimal rejection bandwidth are designed using parallel-coupled stepped impedance resonators (SIRs). The fundamental (f/sub o/) and higher order resonant harmonics of an SIR are analyzed against the length ratio of the high-Z and low-Z segments. It is found that an optimal length ratio can be obtained for each high-Z to low-Z impedance ratio to maximize the upper rejection bandwidth. A tapped-line input/output structure is exploited to create two extra transmission zeros in the stopband. The singly loaded Q(Q/sub si/) of a tapped SIR is derived. With the aid of Q/sub si/, the two zeros can be independently tuned over a wide frequency range. When the positions of the two zeros are purposely located at the two leading higher order harmonics, the upper rejection band can be greatly extended. Chebyshev bandpass filters with spurious resonances up to 4.4f/sub o/, 6.5f/sub o/, and 8.2f/sub o/ are fabricated and measured to demonstrate the idea.     

Latchup-free ESD protection design with complementary substrate-triggered SCR devices

The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.     

ESD protection design to overcome internal damage on interface circuits of a CMOS IC with multiple separated power pins

This paper reports a real case of electrostatic discharge (ESD) improvement on a complementary metal oxide semiconductor integrated circuit (IC) product with multiple separated power pins. After ESD stresses, the internal damage have been found to locate at the interface circuit connecting between different circuit blocks with different power supplies. Some ESD designs have been implemented to rescue this IC product to meet the required ESD specification. By adding only an extra ESD clamp N-channel metal oxide semiconductor with a channel width of 10 /spl mu/m between the interface node and the ground line, the human-body-model (HBM) ESD level of this IC product can be improved from the original 0.5 to 3 kV. By connecting the separated vertical sync signal (VSS) power lines through the ESD conduction circuit to a common VSS ESD bus realized by the seal ring, the HBM ESD level of the enhanced version IC product with 12 separated power supplies pairs can be significantly improved from original 1 kV up to > 5 kV, without the noise coupling issue.     

A robust classification procedure based on mixture classifiers and nonparametric weighted feature extraction

There are many factors to consider in carrying out a hyperspectral data classification. Perhaps chief among them are class training sample size, dimensionality, and distribution separability. The intent of this study is to design a classification procedure that is robust and maximally effective, but which provides the analyst with significant assists, thus simplifying the analyst's task. The result is a quadratic mixture classifier based on Mixed-LOOC2 regularized discriminant analysis and nonparametric weighted feature extraction. This procedure has the advantage of providing improved classification accuracy compared to typical previous methods but requires minimal need to consider the factors mentioned above. Experimental results demonstrating these properties are presented.     

High-resolution electron microscopy of the twinning and intergrowth in Ca4Al6SO16 and Ca3SrAl6SO16

The microstructures of unhydrated calcium aluminosulphate Ca₄Al₆SO₁₆ and Ca₃SrAl₆SO₁₆ have been studied by high-resolution electron microscopy (HREM). The results showed that twinning and twinned slabs could be introduced taking the [1 1 2] direction as the twin axis so that it seems to be coincident with the law of twinning formed in body-centred cubic structures. A previously reported superlattice with a repeat period twice that of the fundamental structure along the 〈1 1 0〉 direction has also been found in both matrix and twin variants. The close intergrowth of Ca₃SrAl₆SO₁₆ and another phase, possibly Sr₃Al₂O₆ existing as an inclusion between these two twin variants, was determined and clearly revealed by electron diffraction and HREM images. The coherent interphase boundaries and orientation relationship between them can also be deduced.     

Mathematical foundations for error estimation in numericalsolutions of integral equations in electromagnetics

The problem of error estimation in the numerical solution of integral equations that arise in electromagnetics is addressed. The direct method (Green's theorem or field approach) and the indirect method (layer ansatz or source approach) lead to well-known integral equations both of the first kind [electric field integral equations (EFIE)] and the second kind [magnetic field integral equations (MFIE)]. These equations are analyzed systematically in terms of the mapping properties of the integral operators. It is shown how the assumption that field quantities have finite energy leads naturally to describing the mapping properties in appropriate Sobolev spaces. These function spaces are demystified through simple examples which also are used to demonstrate the importance of knowing in which space the given data lives and in which space the solution should be sought. It is further shown how the method of moments (or Galerkin method) is formulated in these function spaces and how residual error can be used to estimate actual error in these spaces. The condition number of all of the impedance matrices that result from discretizing the integral equations, including first kind equations, is shown to be bounded when the elements are computed appropriately. Finally, the consequences of carrying out all computations in the space of square integrable functions, a particularly friendly Sobolev space, are explained     

A BiCMOS dynamic carry lookahead adder circuit for VLSIimplementation of high-speed arithmetic unit

A BiCMOS dynamic carry lookahead circuit that is free from race problems is presented. A 16 b full-adder test circuit, which has been designed based on a 2 μm BiCMOS technology, shows a more than five times improvement in speed as compared to the CMOS Manchester carry lookahead (MCLA) circuit. The speed advantage of the BiCMOS dynamic carry lookahead circuit is even greater in a 32- or 64-b adder     

Cluster analysis in industrial market segmentation through artificial neural network

Market segmentation has commonly applied cluster analysis. This study intends to make the comparison of conventional two-stage method with proposed two-stage method through the simulated data. The proposed two-stage method is the combination of self-organizing feature maps and K-means method. The simulation results show that the proposed scheme is better than the conventional two-stage method based on the rate of misclassification.