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Detector jitter, the random delay from the time a photon is incident on a single-photon-counting detector (SPD) to the time an electrical pulse is produced in response to that photon, is characterized for a number of SPDs. The jitter is modeled as a weighted sum of Gaussians. The performance in detector jitter is measured by determining the capacity of a communications channel utilizing a given detector. It is observed that the loss, measured as the ratio of the signal power required to achieve a specified capacity in the presence of jitter to that in the absence of jitter, goes as the square of the normalized jitter standard deviation (the standard deviation of the jitter in slotwidths). The loss is small when the normalized jitter is less than one, and becomes significant beyond that point. This loss must be taken into account when evaluating detectors for very high throughput channels.  相似文献   
2.
Significant technological advances were made toward utilizing the Hale telescope for receiving the faint laser communication signals transmitted from an optical transceiver on a spacecraft orbiting Mars. The so-called Palomar receive terminal design, which would have supported nominal downlink data rates of 1-30 Mbps, is described. Testing to validate technologies for near-Sun (3deg from edge of solar disc) daytime operations is also discussed. Finally, a laboratory end-to-end link utilizing a 64-ary pulse-position modulated photon-counting receiver and decoder that achieved predicted near-capacity (within 1.4 dB) performance is described.  相似文献   
3.
The National Aeronautics and Space Administration has developed a capacity approaching modulation and coding scheme that comprises a serial concatenation of an inner accumulate pulse-position modulation (PPM) and an outer convolutional code [or serially concatenated PPM (SCPPM)] for deep-space optical communications. Decoding of this code uses the turbo principle. However, due to the nonbinary property of SCPPM, a straightforward application of classical turbo decoding is very inefficient. Here, we present various optimizations applicable in hardware implementation of the SCPPM decoder. More specifically, we feature a Super Gamma computation to efficiently handle parallel trellis edges, a pipeline-friendly ";maxstar top-2"; circuit that reduces the max-only approximation penalty, a low-latency cyclic redundancy check circuit for window-based decoders, and a high-speed algorithmic polynomial interleaver that leads to memory savings. Using the featured optimizations, we implement a 6.72 megabits-per-second (Mbps) SCPPM decoder on a single field-programmable gate array (FPGA). Compared to the current data rate of 256 kilobits per second from Mars, the SCPPM coded scheme represents a throughput increase of more than twenty-six fold. Extension to a 50-Mbps decoder on a board with multiple FPGAs follows naturally. We show through hardware simulations that the SCPPM coded system can operate within 1 dB of the Shannon capacity at nominal operating conditions.  相似文献   
4.
Two algorithms for characterization of input error events producing specified distance at the output of certain binary-input partial-response (PR) channels are presented. Lists of error events are tabulated for PR channels of interest in digital recording  相似文献   
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