A pseudo‐differential current‐reuse structure for opamp‐sharing pipelined analog‐to‐digital converters

In this paper, a power efficient pseudo‐differential (PD) current‐reuse structure is presented to alleviate the memory effects of opamp‐sharing in pipelined analog‐to‐digital converters. To implement the PD current‐reuse structure, a switched‐capacitor circuit is introduced for multiplying digital‐to‐analog converter, which has a slight modification compared with the conventional switching scheme with no power penalty. In the proposed multiplying digital‐to‐analog converter circuit, the common‐mode offset amplification of the PD structures is eliminated. Moreover, a PD current‐reuse amplifier is developed from the telescopic structure with an inverter‐based gain‐boosting circuit. The effectiveness of the proposed structure is evaluated in comparison with existing current‐reuse techniques. Copyright © 2014 John Wiley & Sons, Ltd.     

A single-stage operational amplifier with enhanced transconductance and slew rate for switched-capacitor circuits

The DVB-T2 standard for digital terrestrial broadcasting supports the use of quadrature amplitude modulation constellations where the constellation points are rotated in the I–Q plane. This combined with a cyclic delay of the Q component provides improved performance in some fading channels. The complexity of the optimal demapping process for rotated constellations is however significantly higher than for non-rotated constellations. This makes the DVB-T2 demapper one of the most computationally complex parts of a receiver. In this article, we examine possible simplifications of the demapping process suitable for implementation on a general purpose computer containing a modern graphics processing unit (GPU). Furthermore, we measure the performance in terms of throughput, as well as accuracy, of the implemented algorithms. The implementations are designed to interface efficiently to a previously implemented real-time capable GPU-based low-density parity-check channel decoder.     

A multi-stage sigma-delta modulator based on noise-coupling and digital feed-forward techniques

This paper presents a new structure for high-resolution, low-power and wideband discrete time multi-stage (DT-MASH) sigma-delta (ΣΔ) modulators. It uses multi-bit digital input feed forward path (DFF) and noise coupling (NC) techniques. With the DFF technique, the modulator does not need a power-consuming analog adder at the quantizer input, and the number of comparators of the quantizer will be reduced significantly. Also, because of the reduced swing of the modulator’s integrators, low power integrators can be used. Using a second-order NC technique with no extra active block, the order of the modulator, which uses some paths between analog stages, is increased, and its performance is improved with zero-optimization of the modulator’s noise transfer function (NTF). Behavioral simulations and extensive mathematical analyses confirm the effectiveness of the proposed structure. The effect of the non-idealities in the DFF and NC paths were considered in the behavioral simulations. To examine its performance, a MASH 2–1 modulator was designed in the circuit level with a 180-nm CMOS technology and 1.8 V power supply. The integrators use a new op-amp switching technique to reduce total power consumption. With an over-sampling ratio (OSR) of 8 for the 10 MHz signal bandwidth, the proposed structure improves the signal-to-noise and distortion ratio (SNDR) by 28 dB compared with a conventional MASH 2–1 structure at approximately the same power consumption and very low complexity.

     

A pseudo-differential MDAC with a gain-boosting inverter for pipelined ADCs

In this paper, a power-efficient pseudo-differential (PD) multiplying digital-to-analog converter (MDAC) is presented for pipelined analog-to-digital converters (ADCs). The proposed MDAC eliminates the explicit common-mode feedback circuit which is required in fully-differential configurations without any power penalty. Furthermore, a new class-AB gain-boosting inverter is proposed to be used in PD MDAC structures for further power saving. This inverter provides dynamic load current with no significant static power consumption and achieves high DC gain using a new gain-boosting technique. To demonstrate the effectiveness of the proposed circuits, they are utilized in the realization of a 1.5-bit/stage 10 bit 100 MS/s pipelined ADC.