An improved technique and experimental results for the extractionof electron and hole mobilities in MOS accumulation layers

For the first time, experimental results are presented for electron and hole mobilities in the electron and hole accumulation layers of a MOSFET for a wide range of doping concentrations. Also presented is an improved methodology that has been developed in order to enable more accurate extraction of the accumulation layer mobility. The measured accumulation layer mobility for both electrons and holes is observed to follow a universal behavior at high transverse electric fields, similar to that observed for minority carriers in MOS inversion layers. At low to moderate transverse fields, the effective carrier mobility values are greater than the bulk mobility values for the highest doping levels. This is due to screening by accumulated carriers of the ionized impurity scattering by accumulated carriers, which dominates at higher doping concentrations. For lower doping levels, surface phonon scattering is dominant at low to moderate transverse fields so that the carrier mobility is below the bulk mobility value     

A physically based compact gate C-V model for ultrathin (EOT /spl sim/1 nm and below) gate dielectric MOS devices

A computationally efficient and accurate physically based gate capacitance model of MOS devices with advanced ultrathin equivalent oxide thickness (EOT) oxides (down to 0.5 nm explicitly considered here) is introduced for the current and near future integrated circuit technology nodes. In such a thin gate dielectric regime, the modeling of quantum-mechanical (QM) effects simply with the assumption of an infinite triangular quantum well at the Si-dielectric interface can result in unacceptable underestimates of calculated gate capacitance. With the aid of self-consistent numerical Schro/spl uml/dinger-Poisson calculations, the QM effects have been reconsidered in this model. The 2/3 power law for the lowest quantized energy level versus field relations (E/sub 1//spl prop/F/sub ox//sup 2/3/), often used in compact models, was refined to 0.61 for electrons and 0.64 for holes, respectively, in the substrate in the regimes of moderate to strong inversion and accumulation to address primarily barrier penetration. The filling of excited states consistent with Fermi statistics has been addressed. The quantum-corrected gate capacitance-voltage (C-V) calculations have then been tied directly to the Fermi level shift as per the definition of voltage (rather than, for example, obtained indirectly through calculation of quantum corrections to the charge centroids offset from the interface). The model was implemented and tested by comparisons to both numerical calculations down to 0.5 nm, and to experimental data from n-MOS or p-MOS metal-gate devices with SiO/sub 2/, Si/sub 3/N/sub 4/ and high-/spl kappa/ (e.g., HfO/sub 2/) gate dielectrics on (100) Si with EOTs down to /spl sim/1.3 nm. The compact model has also been adapted to address interface states, and poly depletion and poly accumulation effects on gate capacitance.     

Interfacial defect states in HfO/sub 2/ and ZrO/sub 2/ nMOS capacitors

A comprehensive analysis of the bump/kink observed in the experimental capacitance-voltage (C-V) curves of HfO/sub 2/ and ZrO/sub 2/ capacitors was performed using self-consistent numerical simulations. Both HfO/sub 2/ samples grown by sputter deposition and grown by metal-organic chemical vapor deposition (MOCVD) were examined. The bumps in the C-V curves were found to be consistent with an interface state centered 0.25 eV above the valence bandedge for the sputter deposited devices, and 0.30 eV above the bandedge for the MOCVD devices. Annealing of the HfO/sub 2/ devices reduced the densities of these traps, but also increased the effective oxide thickness. Similar defect states were detected for the ZrO/sub 2/ devices centered 0.25 eV above the valence bandedge.     

Models for electron and hole mobilities in MOS accumulation layers

We present new physically based effective mobility models for both electrons and holes in MOS accumulation layers. These models take into account carrier-carrier scattering, in addition to surface roughness scattering, phonon and fixed interface charge scattering, and screened Coulomb scattering. The newly developed effective mobility models show excellent agreement with experimental data over the range 1×10¹⁶-4×10¹⁷ cm^-3 for which experimental data are available. Local-field dependent mobility models have also been developed for both electrons and holes, and they have been implemented in the two-dimensional (2-D) device simulators, PISCES and MINIMOS, thus providing for more accurate prediction of the terminal characteristics in deep submicron CMOS devices. In addition, transition region mobility models have been developed to account for the transition in the mobility in going from the accumulation layer in the gate-to-source overlap region to the inversion layer region in the channel     

Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT /spl sim/ 1 nm) SiO/sub 2/ and high-/spl kappa/ gate stacks

Building on a previously presented compact gate capacitance (C/sub g/-V/sub g/) model, a computationally efficient and accurate physically based compact model of gate substrate-injected tunneling current (I/sub g/-V/sub g/) is provided for both ultrathin SiO/sub 2/ and high-dielectric constant (high-/spl kappa/) gate stacks of equivalent oxide thickness (EOT) down to /spl sim/ 1 nm. Direct and Fowler-Nordheim tunneling from multiple discrete subbands in the strong inversion layer are addressed. Subband energies in the presence of wave function penetration into the gate dielectric, charge distributions among the subbands subject to Fermi-Dirac statistics, and the barrier potential are provided from the compact C/sub g/-V/sub g/ model. A modified version of the conventional Wentzel-Kramer-Brillouin approximation allows for the effects of the abrupt material interfaces and nonparabolicities in complex band structures of the individual dielectrics on the tunneling current. This compact model produces simulation results comparable to those obtained via computationally intense self-consistent Poisson-Schro/spl uml/dinger simulators with the same MOS devices structures and material parameters for 1-nm EOTs of SiO/sub 2/ and high-/spl kappa//SiO/sub 2/ gate stacks on (100) Si, respectively. Comparisons to experimental data for MOS devices with metal and polysilicon gates, ultrathin dielectrics of SiO/sub 2/, Si/sub 3/N/sub 4/, and high-/spl kappa/ (e.g., HfO/sub 2/) gate stacks on (100) Si with EOTs down to /spl sim/ 1-nm show excellent agreement.     

Modeling of direct tunneling current through gate dielectric stacks

The direct tunneling current has been calculated for the first time from an inverted p-substrate through different gate dielectrics by numerically solving Schroedinger's equation and allowing for wavefunction penetration into the gate dielectric stack. The numerical solution adopts a first-order perturbation approach to calculate the lifetime of the quasi-bound states. This approach has been verified to be valid even for extremely thin dielectrics (0.5 nm). The tunneling currents predicted by this technique compare well with the WKB solution. Also for the first time investigation of the wavefunction penetration into gate stacks and their effects on quantization in the substrate has also been performed. For the same effective oxide thickness (EOT) the direct tunneling current decreases with increasing dielectric constant, as expected. However, in order to take full advantage of using high-K dielectrics as gate insulators the interfacial oxide needs to be eliminated     

A novel Si/SiGe heterojunction pMOSFET with reduced short-channeleffects and enhanced drive current

A novel Si/SiGe bandgap engineered pMOSFET structure, called a high mobility heterojunction transistor (HMHJT), is proposed. Reduced short-channel effects and high drive current are predicted in this new device. Simulation results of devices with 100-nm physical gate lengths are presented. Physical effects are illustrated, and the performance is compared to the conventional Si devices. For low standby power or low leakage (high V_T) applications, the off-state leakage current due to drain induced barrier lowering (DIBL) or bulk punchthrough is substantially suppressed, and a very high I_on/I_off ratio of 6×10⁷ is obtained in a HMHJT without any anti-punchthrough implant. This ratio is a factor of 180 higher than that of a fabricated, conventional Si device with a similar threshold voltage found in the literature. On the other hand, for lower operating power (low V_T) applications, an HMHJT has a drive current 80% higher compared to an optimized Si device, while satisfying the same criteria for the off-state leakage current     

Understanding the effects of wave function penetration on theinversion layer capacitance of NMOSFETs

A comprehensive analysis of the effects of wave function penetration on the capacitance of NMOS capacitors has been performed for the first time, using a self-consistent Schrodinger-Poisson solver. The study reveals that accounting for wave function penetration into the gate dielectric causes carrier profile to be shifted closer to the gate dielectric reducing the electrical oxide thickness. This shift increases with increasing gate voltage. For example, in one simulation, the peak is shifted by about 0.2 nm at a surface field of 1.96 MV/cm and 0.33 nm at a surface field of 3.7 MV/cm. This shifting results in all increased capacitance. The increase in capacitance observed in the inversion region is relatively insignificant when a poly gate electrode with a doping of less than 1×10²⁰ cm^-3 is used due to the poly-depletion effect. A physical picture of the effect of physical thickness on the tunneling current is also presented