A 2.7-V CMOS single-chip baseband processor for CT2/CT2+ cordlesstelephones

A low-voltage, low-power CMOS single-chip baseband processor for CT2 and CT2+ cordless telephones is presented. The chip integrates a complete voiceband codec, a tone generator, a G721 adaptive differential pulse code modulation coder/decoder, a burst-mode logic controller for CT2/CT2+ framings, and an I/Q baseband signal generator. The only external components are made of two quartz crystals. The chip is interfaced with standard microcontrollers through a parallel interface. With a 2.7 V minimum supply, it consumes normal and standby powers of 35 mW and 25 μW, respectively. Maximum supply is 5.5 V, and temperature range is from -40 to 70°C. Chip area (including scribe line) is 55.5 mm² in a 0.8 μm N-well double-metal single-poly CMOS process with implanted capacitors     

A -80 dB THD, 4 Vpp switched capacitor filter for 1.5 Vbattery-operated systems

A fully differential fifth-order SC filter that can operate from power supplies as low as 1.5 V featuring a -80 dB THD up to 4 V_pp output voltage is presented. A measured p-weighted noise of 120 μV_rms leads to a dynamic range of 81.5 dB. This circuit is used as reconstruction filter for a low voltage 14-b DAC. The very low voltage operation has been possible by integrating a regulated voltage-multiplier on the same chip. The filter active area is 0.54 mm ² in a 0.8 μm CMOS technology. Typical power consumption is 0.8 mW at 1.5 V supply     

A 3 V 10 MHz pseudo-differential SC bandpass filter using gainenhancement replica amplifier

This paper describes the design strategy and implementation of a high frequency low voltage pseudo-differential SC filter which use opamps with gain enhancement replica amplifier. Experimental results of a biquad SC bandpass with a center frequency of 10 MHz and a Q of 10 are presented. The realized opamp has an open-loop unity-gain bandwidth of 850 MHz, a phase margin of about 62°, and a dc gain of 50 dB. The prototype filter dissipates 23 mW from a 3 V supply and occupies 0.3 mm ² in a 0.8 μm N-well single-poly, double-metal CMOS process     

Tutorial review: audio amplifiers in mobile platforms

Feature phones, smart phones, PDAs and many other similar apparatus are becoming a real presence in every day??s life. This convergence of features broadens the audio demands on the system and increases the difficulties to solve audio problems. Class D speaker amplifiers are becoming the de facto standard for smart phones and feature rich phones due to their high efficiency. However the switching nature of these circuits, the availability of supplies required to provide high power and the intrinsic worst linearity compared to linear amplifiers, have lead the designer to find new architectures and topologies in order to solve those issues. An overview on Class D amplifiers implementation for mobile phones and last design solution is provided in this paper.     

Sliding mode audio class-D amplifier for portable devices

Audio class-D amplifiers are widely used in industrial and consumer portable electronic devices, such as mobile phones, thanks to their high efficiency. However, these amplifiers have a limited linearity due to their switching behavior and also a limited control bandwidth. To overcome these major drawbacks, this paper introduces a self-oscillating control technique based on the sliding mode theory which combines a large control bandwidth and a spread spectrum technique. A high power supply rejection, which is a crucial parameter in modules directly connected to a noisy battery, has also been achieved by introducing a variable hysteresis window. Theoretical analysis, behavioral and electrical simulations are discussed in detail in this paper. An integrated circuit using 0.13 μm CMOS process has been realized focused on mobile phone applications (0.8 W, 3.6 V and 8 Ω). The audio amplifier achieves 97 dB(A) signal-to-noise ratio, 0.02 % harmonic distortion and up to 80 dB of power supply rejection. The die area is smaller than 0.4 mm² while keeping more than 90 % efficiency at 1 W.     

Low-voltage double-sampled ΣΔ converters

An obvious way of achieving higher signal-to-noise ratio in oversampled data converters is by increasing the effective sampling rate. If all other components are kept constant, this translates into integrators with larger bandwidth that in turn results in higher overall power consumption. This work introduces the fully floating switched-capacitor configuration as a simple and robust technique to effectively double the sampling rate of oversampled data converters without compromising any aspect of the performance and yet maintaining the power levels of the conventional approach. The use of internal decimation in the switched-capacitor ladder structure of the digital-to-analog converter further helps in achieving the power budget goals. These converters have been implemented with circuitry capable of operating at a minimum supply voltage of 1.8 V under worst case process and temperature conditions and using clock bootstrapping for the transfer gates. The bootstrapping circuit described here uses a single internal capacitor and has functionality that limits the maximum clock voltage to safe levels under a wide range of supply voltages. The prototype was fabricated in a 0.5-μm CMOS double-poly technology. The analog-to-digital converter occupies a die area of 0.11 mm² dissipating 550 μW while the digital-to-analog converter occupies 0.28 mm² dissipating 600 μW     

A 2.7-V 11.8-mW baseband ADC with 72-dB dynamic range for GSMapplications

A receive baseband analog-to-digital converter (ADC) for a GSM cellular radio system is presented. Low voltage and low power techniques have been applied across many aspects of the design. The circuit consists of two second-order double-sampled semi-bilinear ΣΔ modulators followed by two 576-tap digital finite-impulse response (FIR) GSM-channel filters with offset calibration. The complete ADC achieves a dynamic range of 72 dB and dissipates 11.8 mW from a 2.7-V supply. The area is 1.6 mm² in a 0.5-μm n-well double-poly triple-metal CMOS process