Coupling ratio control of polymeric waveguide couplers by bending

Directional couplers are successfully fabricated on acrylic substrates using polymers synthesised from deuterated methacrylate and deuterated fluoromethacrylate monomers. The excess loss of a 50 mm long coupler is about 0.7 dB including waveguide and fibre coupling losses. A novel method is proposed for tuning the coupling ratio. By bending the coupler, high precision control of within 1% is attained without optical polarisation dependence.<>     

Dynamic MR hepatocholangiography with the SIP Fast GRE (saturation inversion projection fast gradient echo) method

The purpose of this study was to assess the utility of dynamic MR hepatocholangiography with the Gd-EOB-DTPA enhanced SIP Fast GRE sequence in the hepatobiliary system. The SIP Fast GRE sequence was used for sequential imaging of the hepatobiliary system with a frame rate of 3 sec in a 256 x 192 matrix. Dynamic sequential acquisition was performed for 51 min before and after the injection of 30 mu mol/kg of Gd-EOB-DTPA in a rabbit. Dynamic images of the hepatobiliary system were obtained in the rabbit study. Dynamic MR hepatocholangiography provides better functional information than conventional MR cholangiography.     

New chemical etching solution for InP and GaInAsP gratings

A new chemical etching solution of bromine-water system, which is suitable for transforming the fine resist grating mask pattern onto InP and GaInAsP surfaces, is reported. The Br2:H2O:H3PO4 (or HCl) solution does not dissolve AZ 1350 photoresist and exhibits both moderate etching rate and a pit-free etched surface.     

Low-loss optical glass fibre with Al2O3-SiO2 core

Optical glass fibres, consisting of an Al2O3-SiO2 core and SiO2 cladding, were produced by using a glass growth technique of vapour deposition in a flame. The core measured from 4 to 10 ? in diameter, and the difference in refractive index between the core and the cladding was 0.003. The lowest loss of this fibre was 10 dB/km at 0.66 ?m.     

An experimental 1.5-V 64-Mb DRAM

Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns was achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V_CC voltage generator with a current-mirror amplifier and tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades was realized. A word-line driver with a charge-pump circuit was developed to achieve a high boost ratio. A ratio of about 1.8 was obtained from a power supply voltage as low as 1.0 V. A 1.28 μm² crown-shaped stacked-capacitor (CROWN) cell was also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5 V 64 Mb DRAM was designed and fabricated with these technologies and 0.3 μm electron-beam lithography. A typical access time of 70 ns was obtained, and a further reduction of 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAMs, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAMs. This indicates that a low-voltage battery operation is a promising target for future DRAMs     

InGaAs avalanche photodiode with InP p-n junction

A new InGaAs avalanche photodiode structure that has an InGaAs light absorption region and InP avalanche multiplying region is proposed. A dark-current density of 2.2 × 10?3 A/cm2 at 90% of breakdown voltage and a multiplication factor of 45 were obtained for the new structure diode fabricated from a liquid-phase epitaxially grown wafer.     

High reliability silica-based PLC 1×8 splitters on Si

The authors describe the reliability of silica-based PLC 1×8 splitters, which was investigated with reference to the Bellcore requirements. All of the 19 1×8 splitters that were tested satisfy the Bellcore optical criteria after 5000 h at 75°C and 90% RH     

A 5-GByte/s data-transfer scheme with bit-to-bit skew control forsynchronous DRAM

This paper describes a 5-GByte/s data-transfer scheme suitable for synchronous DRAM memory. To achieve a higher data-transfer frequency, the properties were improved based on the frequency analysis of the memory system. Then, a bit-to-bit skew compensation technique that eliminates incongruent skew between the signals is described with a new, multioutput controlled delay circuit to accomplish bit-to-bit skew compensation by controlling transmission timing of every data bit. Simulated maximum data-transfer rate of the proposed memory system resulted in 5.1/5.8 GByte/s (321/365 MHz, ×64 bit, double data rate) for data write/read operation, respectively     

The impact of data-line interference noise on DRAM scaling

A kind of data-line (DL) interference noise in a scaled DRAM cell array is found and studied through analysis. The dynamic behavior of cell arrays due to sense-amplifier operation is derived analytically. Analysis shows that the amount of interference noise is more than three times larger than expected from simple data-line coupling. A novel experimental technique for precise noise determination is developed to verify the analysis. Analytical results are in good agreement with the experimental data. It is found that the interference noise plays a dominant role in determining the operating margin of the DRAM and that a novel process or a cell array architecture for minimizing the interference noise is indispensable in 16-Mb DRAM and beyond