Degradation of bipolar transistor current gain by hot holes duringreverse emitter-base bias stress

Experimental evidences are given which demonstrate that degradation of the common-emitter forward current gain h_FE of submicron silicon npn bipolar transistors at low reverse emitter-base junction applied voltage is caused by primary hot holes of the n⁺ /p emitter tunneling current rather than secondary hot electrons generated by the hot holes or thermally-generated hot electrons. Experiments also showed similar kinetic energy dependence of the generation rate of oxide/silicon interface traps by primary hot electrons and primary hot holes. Significant h_FE degradation was observed at stress voltages less than 2.4 V     

Measurement of the interface trap and dielectric charge density in high-/spl kappa/ gate stacks

We demonstrate an accurate measurement of the interface trap density and the stress-induced dielectric charge density in Si/high-/spl kappa/ gate dielectric stacks of metal-oxide-semiconductor field-effect transistors (MOSFETs) using the direct-current current-voltage (DCIV) technique. The capture cross section and density of the interface traps in the high-/spl kappa/ gate stack were found to be similar to those of the Si/SiO/sub 2/ interface. A constant-voltage stress of the p-channel MOSFET in inversion is shown to result in a negative dielectric charging and an increase in the interface trap density.     

Profiling interface traps in MOS transistors by the DCcurrent-voltage method

Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peaked in drain junction space-charge layer and nonconstant in channel. The interface trap densities were monitored by MOS transistor's d.c. body current and the density profiles were obtained from the body-drain and body-source differential conductance versus drain or source bias voltage. An experimental demonstration is given for a 1.6 μm n-channel Si MOS transistor with about 10¹¹ traps/cm² generated by channel hot electron stress     

Direct-current measurements of oxide and interface traps onoxidized silicon

A direct-current current-voltage (DCIV) measurement technique of interface and oxide traps on oxidized silicon is demonstrated. It uses the gate-controlled parasitic bipolar junction transistor of a metal-oxide-silicon field-effect transistor in a p/n junction isolation well to monitor the change of the oxide and interface trap density. The dc base and collector currents are the monitors, hence, this technique is more sensitive and reliable than the traditional ac methods for determination of fundamental kinetic rates and transistor degradation mechanisms, such as charge pumping     

A unifying study of tandem-junction,front-surface-field,and interdigitated-back-contact solar cells

A theoretical-experimental study of tandem-junction, front-surface-field, and interdigitated-back-contact solar cells is presented. The approach taken in the theoretical analysis emphasizes detailed qualitative physical reasoning which leads to quantitative results. This approach enables the three-dimensional boundary-value problems describing these solar cells to be made tractable. A major result is a unifying view of the physics underlying the performance of these cells. The important physical mechanisms are identified and described, and cell design considerations and trade-offs are discussed.     

Applications of DCIV method to NBTI characterization

The DCIV method was applied to investigate negative bias temperature instability (NBTI) in SiO₂ gate oxides. The DCIV technique, which measures the interface defect density independently from bulk oxide charges, delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift, ΔV_TH. The DCIV results obtained during both stress and relaxation phases are generally consistent with the main features of the reaction–diffusion (R–D) model, which suggests positive charge generation/annealing at the Si/SiO₂ interface due to breaking/re-passivation of the Si–H bonds. These results are in agreement with the spin-dependent recombination (SDR) experiments, which reflect the density of the Si dangling bonds at the Si/SiO₂ interface (P_b centers) and its vicinity (E′ centers). Comparison of degradation kinetics as measured by DCIV, charge-pumping, and I_D − V_G (ΔV_TH) techniques, however, suggests that ΔV_TH includes additional contributions, most likely from the oxide bulk charges. For comparison, an NBTI study was also performed on the high-k HfO₂/SiO₂ gate stacks. After adjusting for the high-k related contribution, similar kinetics of the long-term stress interface trap generation was observed in SiO₂ and high-k gate stacks suggesting a common mechanism of the interface degradation.     

Comparison of time-to-failure of GeSi and Si bipolar transistors

The effects of Ge in the epitaxial-base on the reliability of Si/Ge_xSi_1-x/Si heterojunction bipolar transistors were investigated. The ten-year time-to-failure under emitter-base junction reverse-bias stress was measured at the designed operation voltage by the current-acceleration method and compared to that of Si bipolar junction transistors with no Ge (x=0). The investigation shows that the Ge incorporated by the reduced pressure chemical vapor deposition epitaxial technology to give the ramp-type Ge profile has no adverse effects on the transistor reliability     

Low frequency conductance voltage analysis of Si/GexSi1-x/Si heterojunction bipolar transistors

Low-frequency-conductance-voltage (LFGV) method for analysis of heterojunction bipolar transistors (HBTs) is presented. The method gives accurate quantitative values for the important minority-carrier transport parameters that underlie the transistor performance, such as the base diffusion length, lifetime, diffusion coefficient and transit time. The method also allows a detailed analysis of the current gain and emitter injection efficiency. The analytical model and experimental methodology are demonstrated for a Si/Ge_xSi_1-x/Si HBT with a trapeziodal and linearly graded Ge profiles in the base. The LFGV method is general and can be applied to other bipolar transistors, including those based on III-V materials     

Minority-carrier transport parameters in n-type silicon

Minority-carrier diffusion length L, lifetime τ, and diffusion coefficient D in n-type Si are measured at 296 K in the doping range from 10¹⁸ cm^-3 to 7×10¹⁹ cm^-3. The measurement is based on a lateral collection of carriers generated by a spatially uniform light. The distance between the illumination edge and the collection junction is defined by photolithography. This allows simultaneous and independent determination of all transport parameters in the same material. A self-consistency and accuracy check is provided by the relation L ²=Dτ. Details of experimental procedures are described. Empirical best-fit relations for the three parameters are given. The extraction of lifetime and diffusion coefficient was done in the frequency domain, which allows for straightforward elimination of parasitic effects in the nanosecond and subnanosecond range     

Accelerated reverse emitter-base bias stress methodologies andtime-to-failure application

A second current-acceleration method for measuring the reliability of silicon bipolar transistors under reverse emitter-base bias stress is demonstrated in this paper. The low-voltage operation condition in submicron transistors may be attained during the stress experiments, providing an accurate determination of the transistor's operation time-to-failure (TTF) without extrapolating from higher voltage stress data. Two different current-acceleration stress methods are demonstrated in one transistor design and compared with the traditional voltage-acceleration method using the carrier kinetic energy as the independent variable. It is shown that the traditional voltage-acceleration method can give an erroneous and larger extrapolated time-to-failure by several orders of magnitude in some devices