Analysis, design, and optimization of spiral inductors andtransformers for Si RF ICs

Silicon integrated circuit spiral inductors and transformers are analyzed using electromagnetic analysis. With appropriate approximations, the calculations are reduced to electrostatic and magnetostatic calculations. The important effects of substrate loss are included in the analysis. Classic circuit analysis and network analysis techniques are used to derive two-port parameters from the circuits. From two-port measurements, low-order, frequency-independent lumped circuits are used to model the physical behavior over a broad-frequency range. The analysis is applied to traditional square and polygon inductors and transformer structures as well as to multilayer metal structures and coupled inductors. A custom computer-aided-design tool called ASITIC is described, which is used for the analysis, design, and optimization of these structures. Measurements taken over a frequency range from 100 MHz to 5 GHz show good agreement with theory     

Controlled release of fluorouracil (5-FU) from chitosan-co-poly(ethylene glycol)/ poly(glycerol sebacate)-co-poly(ethylene glycol)-coated iron oxide

A blend of polyglycerol sebacate-poly ethylene glygol/chitosan-poly ethylene glycol-coated iron oxide (PGS-PEG/CS-PEG@Fe₃O₄) nanoparticles for 5FU delivery was prepared by reverse ultrasonic emulsification method. To enhance polymers’ solubility, PEG was grafted. Chemical characterization was performed through Fourier transformed infrared and proton nuclear magnetic resonance spectra. In vitro assay revealed that release profile of 5FU-loaded PGS-PEG/CS-PEG@Fe₃O₄ is sustained. Moreover, cytotoxicity was analyzed on HT29 cell line at the presence of external magnetic field using the lactate dehydrogenase and Alamar Blue. Results illustrate that (PGS-PEG/CS-PEG@Fe₃O₄) is promising to use as a carrier for 5FU anticancer agent with sustained tailored release.     

A Highly Linear Broadband CMOS LNA Employing Noise and Distortion Cancellation

A broadband inductorless low-noise amplifier (LNA) design that utilizes simultaneous noise and distortion cancellation is presented. Concurrent cancellation of the intrinsic third-order distortion from individual stages is exhibited with the common-gate and common-source cascade. The LNA is then limited by the second-order interaction between the common source and common gate stages, which is common in all cascade amplifiers. Further removal of this third-order distortion is achieved by incorporating a second-order-distortion-free circuit technique in the common gate stage. Implemented in 0.13 m CMOS technology, this LNA achieved 16 dBm in both the 900 MHz and 2 GHz bands. Measurements demonstrate that the LNA has a minimum internal gain of 14.5 dB, noise figure of 2.6 dB from 800 MHz to 2.1GHz while drawing 11.6 mA from 1.5 V supply voltage.     

Design considerations for 60 GHz CMOS radios

With the availability of 7 GHz of unlicensed spectrum around 60 GHz, there is a growing interest in using this resource for new consumer applications requiring very high-data-rate wireless transmission. Historically, the cost of the 60 GHz electronics, implemented in the compound semiconductor technology, has been prohibitively expensive. A fully integrated CMOS solution has the potential to drastically reduce costs enough to hit consumer price points. System, circuit, and device-level barriers to a low-cost 60 GHz CMOS implementation are described, potential solutions are explored, and remaining challenges are discussed.     

9.6/4.8 GHz dual-mode voltage-controlled oscillator with injection locking

A prototype dual-mode voltage-controlled oscillator supporting two simultaneous oscillation modes is fabricated and demonstrated in a 0.18 mum CMOS process. The oscillator has two resonant ports while sharing one bias. Injection locking is applied to lock the low frequency, 4.8 GHz, to half of the high frequency, 9.6 GHz. The oscillator core consumes 7 mA from a 1.8 V supply. Measurement shows a tuning range of 5% and phase noise is -103 and -109 dBc/Hz measured at 1 MHz offset from the high and low frequency tones, respectively     

Ladder-shaped network for ESD protection of millimetre-wave CMOS ICs

A compact ladder-shaped electrostatic discharge (ESD) protection circuit is presented for millimetre-wave integrated circuits (ICs) in CMOS technology. Multiple shorted shunt stubs form a ladder network together with series stubs as ESD protection that discharges current/voltage pulses caused by an ESD event, while at the same time the network is embedded as part of the matching circuit for a normal operation. A 60 GHz low-noise amplifier using a 90 nm CMOS process is demonstrated with the proposed ESD protection methodology that introduces less than 1 dB insertion loss. Owing to the ESD current distribution through multiple shorted stubs, the proposed methodology is useful to millimetre-wave ICs with advanced CMOS technology that suffers from higher sheet resistance of the metal layers.     

Fully Integrated CMOS Power Amplifier With Efficiency Enhancement at Power Back-Off

This paper presents a new approach for power amplifier design using deep submicron CMOS technologies. A transformer based voltage combiner is proposed to combine power generated from several low-voltage CMOS amplifiers. Unlike other voltage combining transformers, the architecture presented in this paper provides greater flexibility to access and control the individual amplifiers in a voltage combined amplifier. In this work, this voltage combining transformer has been utilized to control output power and improve average efficiency at power back-off. This technique does not degrade instantaneous efficiency at peak power and maintains voltage gain with power back-off. A 1.2 V, 2.4 GHz fully integrated CMOS power amplifier prototype was implemented with thin-oxide transistors in a 0.13 mum RF-CMOS process to demonstrate the concept. Neither off-chip components nor bondwires are used for output matching. The power amplifier transmits 24 dBm power with 25% drain efficiency at 1 dB compression point. When driven into saturation, it transmits 27 dBm peak power with 32% drain efficiency. At power back-off, efficiency is greatly improved in the prototype which employs average efficiency enhancement circuitry.     

Kinetic and thermodynamic studies of AISI 4130 steel alloy corrosion in ethylene glycol-water mixture in presence of inhibitors

The electrochemical behavior of steel alloy in ethylene glycol-water mixture was investigated by electrochemical methods. The results obtained showed that corrosion rate was decreased with increasing ethylene glycol concentration. The effect of inorganic inhibitors including NO₃ ^?, NO₂ ^?, Cr₂O₇ ^2? and CrO₄ ^2? were studied using electrochemical techniques where the highest inhibition efficiency was obtained for CrO₄ ^2?. In the presence of chromate the inhibitor efficiency increased with its concentration. The inhibiting effect of the chromate was explained on the basis of the competitive adsorption between the inorganic anions and the aggressive Cl^? ions, and the adsorption isotherm basically obeys the Langmuir adsorption isotherm. Thermodynamic parameters for steel corrosion and inhibitor adsorption were determined and reveal that the adsorption process is spontaneous. Also, a phenomenon of both physical and chemical adsorption is proposed.     

An ultrawideband CMOS low-noise amplifier for 3.1-10.6-GHz wireless receivers

An ultrawideband 3.1-10.6-GHz low-noise amplifier employing an input three-section band-pass Chebyshev filter is presented. Fabricated in a 0.18-/spl mu/m CMOS process, the IC prototype achieves a power gain of 9.3 dB with an input match of -10 dB over the band, a minimum noise figure of 4 dB, and an IIP3 of -6.7 dBm while consuming 9 mW.     

Analysis and Design of RF CMOS Attenuators

Attenuators are analyzed for their minimum Insertion Loss (IL), maximum attenuation and source-load matching performance. These results are used to make trade-offs in the design of a CMOS attenuator with wide dynamic range, designed and fabricated in a 0.13 mum CMOS process. The design employs two non-identical cascaded T-stages that are activated consecutively to improve linearity. The design operates in the frequency band of DC-2.5 GHz with 0.9-3.5 dB insertion loss and 42 dB maximum attenuation in the entire frequency range. Worst case S11 is - 8.2 dB across the frequency band. The design achieves an IIP3 of + 20 dBm at mid-attenuation.