A Design Methodology for MOS Current-Mode Logic Frequency Dividers

In this work, a methodology for the design of MOS current-mode logic frequency dividers is presented. A mix of hand calculations and circuit simulations is used to relate the power consumption and the frequency of operation. Each latch in the dividers is sized separately in order to minimize the overall power consumption. Furthermore, the effect on the power consumption of circuit parameters such as output swing and voltage gain of the input differential pair is analyzed in detail. The methodology has been applied to dividers by two and dividers by three with 50% output duty cycle     

Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs

This paper presents a modular and comprehensive nonlinear time-domain behavioral model for phase-locked loops (PLLs) that are suitable for analyzing the impact on the output signal of the noise contribution and nonidealities of the constituent building blocks. The model building blocks are described by Simulink submodels and can be configured to implement different PLL topologies. Postprocessing of the PLL output provides the PLL phase noise and spur-to-carrier-ratio performances. The calculated phase-noise spectra are compared with those obtained with the well-known linear model and with measurements. To show the flexibility of this approach, many case studies are reported; among them, the analysis of the spurs due to charge pump mismatch and the transient phase noise, and spurs performances of a PLL featuring a dual control of the voltage-controlled oscillator.      

Experimental comparison of different dead-time correction techniques in single-channel counting experiments

For single-channel counting, the dead-time correction method using transmission formulae was compared experimentally with the live-time technique. Agreement is within 4×10⁻⁴ for count rates up to 10⁴ s⁻¹ when the formulae for dead times in series are used and the dead-time value related to the analogue pulse width is adjusted for the BIPM modules. At higher count rates, a bias of 2×10⁻³ is observed. Two different live-time modules were compared and it was demonstrated that the live-time correction is also sensitive to the analogue pulse width and to the duration or rise time of the clock pulses. When these effects are taken into account, the two modules differ by only 5×10⁻⁴.     

Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture

This paper describes the modeling, design, and characterization of a low-jitter 2.4-GHz LC-VCO PLL architecture realized in a standard 0.12-/spl mu/m CMOS technology. It features an analog dual control loop for fine and coarse VCO tuning that allows very low VCO gain (60 MHz/V) for noise rejection while maintaining a wide tuning range. The coarse input of the VCO is driven by an analog circuit that adjusts the VCO gain in a continuous manner. Measurements demonstrate an integrated jitter of 0.74 ps that is 43% lower compared to results from a standard PLL topology (STD PLL) with a single control loop. The PLLs have the same bandwidth and output frequency range and were built on the same wafer for comparison. The circuit area of the proposed LC-VCO PLL is 0.7 mm/sup 2/ and the power consumption is 32 mW. The area and power consumption of the proposed LC-VCO PLL are less than 1% larger compared to the STD PLL.