A 54.2?μW 5?MSps 9-bit ultra-low energy analog-to-digital converter in 180?nm technology

This paper aims to address the growing need for ultra-low power analog-to-digital converters (ADC). For this purpose, we pushed the limitations of conventional successive approximation register ADCs through the use of deep voltage scaling, a novel iterative precharging scheme, and topological improvements over recent works. From the simulations results we achieve a figure of merit of 31?fJ per conversion step, with an 8.45 effective number of bits, working at 5?MSps.     

Design methodology for configurable analog to digital conversion using support vector machines

We apply a support vector machine (SVM) classifier to the design of analog to digital converters. Each output bit of the converter is the output of a binary classifier, which is a nonlinear SVM. The classifier effectively learns a folding characteristic for each bit, which is realized as the weighted sum of a set of kernel functions. In our proposal, the kernel does not need to be symmetric or positive definite, unlike in the case of a conventional SVM. This makes the approach more amenable to VLSI design, where such constraints are hard to satisfy. The SVM uses a set of binary weights, which allows the folding characteristics to be digitally corrected after fabrication. This facility is of considerable value in analog design in a deep sub micron era, where simulation models do not adequately capture the behavior of devices, or their variations. The proposed methodology reduces design time, can be automated and calibrated for process variations and ageing, by changing a set of digital scaling coefficients.     

Fast feedthrough logic: a high performance logic family for GaAs

A GaAs dynamic logic family using the feedthrough evaluation concept is presented in this paper. Feedthrough logic (FTL) allows the outputs to be partially generated before the input signals arrive. A modified version of this logic, where the function and its complement are implemented in a differential structure, is also introduced. In an FTL gate, the logic outputs are reset to low during the high phase of the clock and evaluated during the low phase of the clock. Resetting to low alleviates the problems of charge sharing and leakage current associated with the other GaAs dynamic logic families. FTL logic functions can be cascaded in a domino-like fashion without a need for the intervening inverters. We employ this novel concept to design several arithmetic circuits. We compare a 4-bit ripple carry adder in FTL with the other published works in terms of device count, area, delay, clock rate and power consumption. The results demonstrate that FTL is the simplest, the fastest, and consumes least power. In addition, our FTL design compares very well with the standard CMOS technology. FTL gates are fully compatible with direct coupled field-effect transistor logic (DCFL), and therefore, can be included in a DCFL standard cell library for improving cell-based ASIC performance. To match the high-speed of the FTL combinational blocks, we present a single-ended latch for pipelining the FTL blocks. Comparisons with the other published results demonstrate the superior performance of our dynamic latch.     

On the design and optimization of symmetric low swing to high swing level converter for on-chip interconnects

This paper reports a series of symmetric high performance, low to full swing level converters (udld1-converter to udld5-converter) for recovering signal levels at the receiver end of the global interconnects with large capacitive loads. The proposed udld5-converter provides a matching receiver for the up-down low swing voltage driver (UDLD) signaling style for driving the global interconnect lines. When implemented on 0.13 μm CMOS 1.2 V technology, the udld5-converter performs 16% faster, reduces the energy per switching event by 4%, the energy-delay product by 19%, and the active area by 10%, when compared with a counterpart up low swing voltage driver (ULD) level converter (uld-converter). The proposed level converter receivers, each provide a different performance energy saving trade off. The paper also provides comparative performance evaluation of the various proposed level converters and uld-converter.     

Application of genetic algorithm in computing the tradeoffs between power consumption versus delay in digital integrated circuit design

This paper presents a novel methodology to obtain the entire power consumption versus delay tradeoff curve for the critical paths of a combinational logic circuit in a very efficient way using the genetic algorithm (GA). In order to evaluate the proposed algorithm the most representative set of two-level and multi-level networks from the MCNC91 benchmark suite were processed. The required computational effort, measured in terms of CPU time, is several times better for the proposed GA optimization technique than liner programming (LP) technique. On the other hand, the optimal design points obtained by the GA and LP techniques are very close to each other to within 0.3%.     

Joint antenna subset selection for spatial multiplexing systems based on statistical and instantaneous selection criteria

While the joint transmit/receive (Tx/Rx) AnSS with exhaustive search is the best solution for error rate minimization, its complexity makes it difficult for implementation on practical systems. To overcome this disadvantage, we propose a two-stage AnSS algorithm for the spatial multiplexing (SM) in the multiple input multiple output (MIMO) system, which employs both the statistical (i.e., average Euclidean distance, AED) and instantaneous selection criteria (i.e., modified instantaneous Euclidean distance, M-IED). The proposed algorithm reduces the computational complexity by decoupling the joint Tx/Rx selection into two separate selections of the numbers of Tx/Rx antennas and antenna subset, respectively. We show that the proposed AED criterion can be implemented through a simple look up table (LUT), thereby significantly reducing the computational complexity. Simulation results and computational complexity comparisons, prove that the proposed two-stage AnSS algorithm for the SM scheme reduces the hardware and computational complexity without any loss of the signal-to-noise ratio (SNR) and the diversity order, compared to the exhaustive search method.     

Dual-mode SM/STBC system with antenna subset selection employing ML detection

Multiple input multiple output (MIMO) antenna system is a promising candidate to meet the demands of 4th Generation (4G) cellular communication systems by offering increased spectral efficiency through the spatial multiplexing (SM) gain, and improved link reliability through the space–time block coding (STBC) diversity gain. This paper presents a new scheme that combines the dual-mode SM/STBC and the antenna subset selection (AnSS) schemes. In the proposed scheme, the combination of the SM/STBC switching and the full antenna subset selection (AnSS) at both the transmitter (Tx) and the receiver (Rx) ends of the communication channel are adaptively selected through a simple algorithm based on the singular values of the channel matrix at the Rx side. Thus, the new scheme achieves the best BER performance over the previous works regardless of the data rate. The simulation results show that the proposed scheme with the full AnSS outperforms the previous works, by up to the 12.5 dB at the bit error rate (BER) of 10^‐5${10}^{‐5}$. Further, a partial AnSS is also proposed which dramatically reduces both the computational complexity (by 31%) and the hardware (by 50%), cost, without any appreciable loss in the BER performance, when compared with the full AnSS.