Bipolar transistor selected P-channel flash memory cell technology

A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed, where a bipolar transistor embedded in the source region of the cell amplifies cell-read-current and acts as a select transistor. With this cell, not only a very low 1.5 V non-word-line-boosting read operation, but also a sector-erase operation are successfully achieved with only a small cell-size increase over the conventional NOR cell. Moreover, this cell technology maintains all the advantages of the P-channel DIvided-bit-line NOR (DINOR) flash memory     

A 0.8-dB insertion-loss, 17.4-dBm power-handling, 5-GHz transmit/receive switch with DETs in a 0.18-/spl mu/m CMOS process

An optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch has been fabricated using depletion-layer-extended transistors (DETs) in a 0.18 /spl mu/m CMOS process. The switch features the highest performance to date of any switch using a CMOS process, of a 0.8 dB insertion-loss, 23 dB isolation and 17.4 dBm power-handling capability at 5 GHz. The low insertion-loss has been achieved with the effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations. The high power-handling capability is owing to the combined effect of the adoption of the source/drain dc biasing scheme and the high substrate resistance in the DET.     

Novel self-limiting high-speed program scheme of p-channel DINORflash memory with n-channel select transistors

This paper describes a novel self-limiting high-speed program scheme of the p-channel DINOR (D_I_vided bit line N_O_R_) flash memory utilizing n-channel select transistors. This scheme makes it possible to maintain the high programming throughput of the p-channel DINOR even for future lower-voltage operation. Using this scheme, programming stops automatically at the desired threshold voltage state without any conventional verify operations. Moreover, the only structural change from the conventional p-channel DINOR is the change of the impurity type of the select transistors, and the only operational change is the addition of a very short negative voltage pulse of 0.1 μs to each programming gate pulse. This shortness of the additional pulse hardly degrades the programming speed at all. This novel scheme is expected to become a key technology for the realization of future, high-performance, lower-supply-voltage p-channel DINOR flash memories     

Device characteristics of 0.35 μm P-channel DINOR flash memoryusing band-to-band tunneling-induced hot electron (BBHE)programming

The P-channel DINOR flash memory, which uses the band-to-band tunneling induced hot electron (BBHE) program method having the advantages of high scalability, high efficiency, and high oxide reliability, was fabricated by 0.35-μm-rule CMOS process and was investigated in detail. An ultra-high programming throughput of less than 8 ns/byte (=4 μs/512 byte) and a low current consumption of less than 250 μA were achieved by utilizing 512-byte parallel programming. Furthermore, we investigated its endurance characteristics up to 10⁶ program/erase cycles, and window narrowing and G_m degradation were found to be very small even after 10⁶ cycles. It is thought that the BBHE injection point contributes to the G _m stability and the oxide-damage-reduced operation contributes to the good window narrowing characteristics. The P-channel DINOR flash memory realizing high programming throughput with low power consumption is one of the strongest candidates for the next generation of high-performance, low-voltage flash memories     

21.5-dBm power-handling 5-GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with depletion-layer-extended transistors (DETs)

This paper reports a 21.5-dBm power-handling 5-GHz transmit/receive CMOS switch utilizing the depletion-layer-extended transistor (DET), which possesses high effective substrate resistance and enables the voltage division effect of the stacked transistor configuration to work in the CMOS switch. Furthermore, low insertion losses of 0.95 and 1.44 dB are accomplished at 5 GHz in the transmit and receive modes, respectively, with the benefit of the insertion-loss improvement effects in the DET. At the same time, high isolations of more than 22 dB were obtained at 5 GHz in the transmit and receive modes with the adoption of the shunt/series type circuit.