Origin of the threshold voltage instability in SiO/sub 2//HfO/sub 2/ dual layer gate dielectrics

The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.     

Accurate Gate Impedance Determination on Ultraleaky MOSFETs by Fitting to a Three-Lumped-Parameter Model atFrequencies From DC to RF

We present an experimental methodology that demonstrates the suitability of the conventional three-lumped- parameter model for gate impedance of MOSFET devices at frequencies from dc to the gigahertz range, which permits accurate extraction of model parameters. The parasitic effects at a high frequency are minimized by using radio frequency techniques (i.e., short return paths and de-embedding structures), whereas a robust parameter extraction algorithm overcomes possible instrument inaccuracies. When combined, these allow simultaneous extraction of all three parameters (i.e., C_gate, R_DT and R_series) from the model. The technique is applied to conventional SiO₂ -based MOSFET devices and to ultraleaky HfO₂ devices with aggressively scaled gate dielectric thickness.     

Mechanism of O2-anneal induced Vfb shifts of Ru gated stacks

A systematic study of the flat-band voltage (V_fb) shift of Ru gated metal-oxide-semiconductor (MOS) capacitors subjected to thermal treatment in O₂ has been performed. The dependence of the V_fb shift on the thickness of Ru, anneal temperature and time is studied. The V_fb shift is ascribed to the shift of metal gates’ work function (WF), and is not significantly dependent on the type of dielectric (HfO₂ or SiO₂). From time-of-flight secondary ion mass spectrometry (TOF-SIMS) measurement, it was found that after thermal treatment in ¹⁸O₂, ¹⁸O penetrated through Ru and was incorporated in the Ru/dielectric interface region. We believe that the formation of the thin interfacial RuO_x layer is responsible for the V_fb shift.     

Stress-induced leakage current (SILC) and oxide breakdown: are theyfrom the same oxide traps?

Many research groups have used stress-induced leakage current SILC as a mean to measure the oxide traps (defects) buildup in the oxide film during electrical stress. It is commonly believed that these very same traps will lead to oxide breakdown when their density reaches a critical value. We studied the annealing kinetic of SILC as well as, the oxide breakdown distribution and found that they are quite different. Our result casts serious doubt on the validity of the popular assumption     

Potential remedies for the VT/Vfb-shift problem of Hf/polysilicon-based gate stacks: a solution-based survey

In this paper, we report on several different approaches that were implemented on both capacitor and scaled planar MOS transistor devices in order to prevent or undo the commonly observed V_T/V_fb-shift and –instability for Hf-based high-κ gate stacks in conjunction with a poly-Si electrode. While the latter issue can eventually be mitigated, the V_T-shift problem jeopardizes initial high-κ integration with poly-Si for the 65 nm and also for the 45 nm node. The different attempts to circumvent this problem include (1) bulk modifications of the high-κ stack/process, (2) the use of various thin capping layers at the poly/high-κ interface and (3) chemical and process modifications of the gate electrode deposition. We have observed that, although considerable improvements have been made in terms of e.g. yield, performance and instability, none of these techniques succeeded in obtaining V_T-values in line with the ITRS device specifications, i.e. avoiding Fermi Level Pinning to occur for poly-Si/Hf(Si)O(N) stacks.     

Reliability screening of high-k dielectrics based on voltage ramp stress

High-k development moves towards integration into CMOS processes rising attention for the reliability assessment. In this paper, the methodology for reliability screening is discussed based on constant voltage stress and voltage ramp stress. It will be shown that both procedures yield equivalent results and the determined reliability parameters are compatible. Better control of the overall measurement time favours the voltage ramp stress as preferred fast screening method for integration of high-k dielectrics.     

Electrical properties of high-κ gate dielectrics: Challenges, current issues, and possible solutions

High-κ gate dielectrics like HfO₂ and HfSiO(N) are considered for the replacement of SiO₂ and SiON layers in advanced complementary metal–oxide–semiconductor (MOS) devices. Using these gate oxides allows indeed to drastically reduce the leakage current flowing through the device, as required by the specifications of the International Technology Roadmap for Semiconductors. However, major problems remain to be solved before the possible use of high-κ gate dielectrics in integrated circuits. The purpose of this paper is to give an overview of the challenges and issues pertaining to high-κ-based devices. Several issues are discussed in detail, like flat-band and threshold voltage control, carrier mobility degradation, charge trapping, gate dielectric wear-out and breakdown, and bias temperature instabilities. Our current understanding of these issues is presented, with an emphasis on the relationship between the material properties of the gate stack, and the electrical properties of the devices. The combination of metal gates with high-κ gate dielectric appears to be a promising solution for the further scaling down of CMOS devices.     

Depassivation of latent plasma damage in devices

While plasma-induced charging damage has been widely studied in recent years, much of the work has concentrated upon the impact on n-channel MOSFET reliability [1–6]. This work focuses the impact of plasma damage on pMOS devices from the viewpoint of oxide trapped charge and interface states with the experimental featuring two parameters Q_p and ΔN_p, linked respectively to the oxide charge and the interface state density. This experimental method is valid for pMOS devices in two different technologies and permits to fully compare devices with different oxide thickness. Furthermore, we demonstrate that, for a given antenna, the plasma damage roughly has the same net impact on transistor characteristics, regardless of oxide thickness.     

Impact of defects on the high-κ/MG stack: The electrical characterization challenge

The integration of high-κ dielectrics in MOSFET devices is beset by many problems. In this paper a review on the impact of defects in high-κ materials on the MOSFET electrical characteristics is presented. Beside the quality of the bulk of the dielectric itself, the interfaces between the high-κ and the interfacial oxide layer and the gate electrode are of crucial importance. When poly-Si is used as gate electrode, the defects at the poly-Si/high-κ interface control the band alignment as well as the gate depletion. The quality and thickness of the interfacial SiO₂ controls both the carrier mobility in the channel as well as the kinetics of charging and discharging of pre-existing high-κ defects. The quality of the interfacial layer has also important consequences for reliability specifications like negative bias instability and dielectric breakdown.     

A study of relaxation current in high-/spl kappa/ dielectric stacks

Dielectric relaxation currents in SiO/sub 2//Al/sub 2/O/sub 3/ and SiO/sub 2//HfO/sub 2/ high-/spl kappa/ dielectric stacks are studied in this paper. We studied the thickness dependence, gate voltage polarity dependence and temperature dependence of the relaxation current in high-/spl kappa/ dielectric stacks. It is found that high-/spl kappa/ dielectric stacks show different characteristics than what is expected based on the dielectric material polarization model. By the drain current variation measurement in n-channel MOSFET, we confirm that electron trapping and detrapping in the high-/spl kappa/ dielectric stacks is the cause of the dielectric relaxation current. From substrate injection experiments, it is also concluded that the relaxation current is mainly due to the traps located near the SiO/sub 2//high-/spl kappa/ interface. As the electron trapping induces a serious threshold voltage shift problem, a low trap density at the SiO/sub 2//high-/spl kappa/ interface is a key requirement for high-/spl kappa/ dielectric stack application and reliability in MOS devices.