PMOS transistors in LPCVD polycrystalline silicon-germanium films

P-channel MOS thin-film transistors (TFTs) have been fabricated in low-pressure chemical vapor deposition (LPCVD) polycrystalline silicon-germanium (poly-SiGe) films using either a low-temperature (⩽600 °C) process or a high-temperature (up to 950°C) process. Poly-SiGe TFT technology allows the use of lower anneal temperatures and shorter anneal times as compared to a poly-Si TFT technology. The devices fabricated show good transistor characteristics after hydrogenation to reduce the number of electrically active traps in their active channel region     

A selectively deposited poly-gate ITLDD process with self-alignedLDD/channel implantation

An inverse-T lightly doped drain (ITLDD) CMOS process which features improved hot-carrier effects and self-aligned source/drain and channel implantation profiles is presented. Compensation effects by the heavy channel doping on the light N^-/P^- profile are minimized in this ITLDD structure, because the implants are self-aligned to the polysilicon-gate edge. In addition, because selective polysilicon deposition rather than an incomplete poly-gate etchback is used to define the ITLDD structure, a simpler, more manufacturable process is obtained due to improved control of the thin poly-gate shelf thickness     

Poly-gate sidewall oxidation induced submicrometer MOSFETdegradation

The effect of poly-gate sidewall oxidation on short-channel MOSFET behavior is examined. The gain, threshold voltage, and apparent electrical channel length are shown to be very sensitive to the location of the n^- junction edge with respect to the poly-gate edge for a lightly-doped-drain NMOS transistor. New guidelines for the design of submicrometer MOSFETs based on an analysis of the sidewall oxidation of the polysilicon after gate definition are proposed     

The effects of boron penetration on p+ polysilicon gatedPMOS devices

The penetration of boron into and through the gate oxides of PMOS devices which employ p⁺ doped polysilicon gates is studied. Boron penetration results in large positive shifts in V_FB , increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF₂ implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi₂ salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO ₂/Si interface     

Disposable polysilicon LDD spacer technology

An advanced 0.5-μm CMOS disposable lightly doped drain (LDD) spacer technology has been developed. This 0.5-μm CMOS technology features surface-channel LDD NMOS and PMOS devices, n⁺/p⁺ poly gates, 125-A-thick gate oxide, and Ti-salicided source/drain/gate regions. Using only two masking steps, the NMOS and PMOS LDD spacers are defined separately to provide deep arsenic n⁺ regions for lower salicided junction leakage, while simultaneously providing shallow phosphorus n^- and boron p^- regions for improved device short-channel effects. Additionally, the process allows independent adjustment of the LDD and salicide spacers to optimize the LDD design while avoiding salicide bridging of source/drain to gate regions. The results indicate extrapolated DC hot-carrier lifetimes in excess of 10 years for a 0.3-μm electrical channel-length NMOS device operated at a power-supply voltage of 3.3 V     

Improved CMOS field isolation using germanium/boron implantation

A novel germanium/boron implantation technique for improving the electrical field isolation of high-density CMOS circuits is demonstrated. Germanium implantation causes a reduction in dopant diffusion and segregation during field oxidation and is shown to increase the p-well field threshold voltage by as much as 40% with no significant degradation to junction or device performance. Selective germanium implantation with a blanket boron field implant can also improve the electrical field isolation behavior for CMOS circuits     

A novel CMOS VLSI isolation technology using selective chlorineimplantation

An isolation technology that uses blanket boron and selective chlorine n-well implantation prior to field oxidation is proposed. Chlorine implantation results in an increase in the thermal-oxidation linear-reaction-rate coefficient by a factor of 11.5, which enhances the segregation of dopant atoms in the n-well field region. Due to the redistribution of dopant atoms in the n-well field region, the field threshold voltage magnitude may be increased by as much as 20 V when chlorine implantation is used     

Electrical properties of heavily doped polycrystallinesilicon-germanium films

The electrical properties of polycrystalline silicon-germanium (poly-Si_1-xGe_x) films with germanium mole fractions up to 0.56 doped by high-dose ion implantation are presented. The resistivity of heavily doped p-type (P⁺) poly-Si_1-x Ge_x is much lower than that of comparably doped poly-Si, because higher levels of boron activation and higher hole mobilities are achieved in poly-Si_1-xGe_x. The resistivity of heavily doped n-type (N⁺) poly-S_1-xGe_x is similar to that of comparably doped poly-Si for x<0.45; however, it is considerably higher for larger Ge mole fractions due to significant reductions in phosphorus activation. Lower temperatures (~500°C), as well as lower implant doses, are sufficient to achieve low resistivities in boron-implanted poly-Si_1-xGe_x films, compared to poly-Si films. The work function of P⁺ poly-Si_1-xGe_x decreases significantly (by up to ~0.4 Volts), whereas the work function of N⁺ poly-Si_1-xGe_x decreases only slightly, as Ge content is increased. Estimates of the energy bandgap of poly-Si_1-xGe_x show a reduction (relative to the bandgap of poly-Si) similar to that observed for unstrained single-crystalline Si_1-xGe_x for a 26% Ge film, and a reduction closer to that observed for strained single-crystalline Si _1-xGe_x for a 56% Ge film. The electrical properties of poly-Si_1-xGe_x make it a potentially favorable alternative to poly-Si for P⁺ gate-material applications in metal-oxide-semiconductor technologies and also for p-channel thin-film transistor applications     

LDD MOSFETs using disposable sidewall spacer technology

A technology for fabricating lightly doped drain (LDD) MOSFET devices based on disposable sidewall spacers is presented. Using a thin polysilicon buffer layer between the low-temperature oxide (LTO) sidewall spacers and the oxidized polysilicon gate, a single masking step can be used to form the n^- and n⁺ or p^- and p⁺ source/drain implants for the NMOS and PMOS devices, respectively. In addition, the LTO sidewall spacers may be removed by a wet HF strip, thus minimizing additional damage to the gate oxide that may be caused by reactive ion etch removal. The disposable sidewall spacer technology is easily adaptable to a CMOS process as demonstrated by the fabrication of a 4 K×4 SRAM circuit using a conventional 1.5-μ CMOS technology     

A physical model for boron penetration through thin gate oxidesfrom p+ polysilicon gates

Based on numerical device and process simulation, it is shown that enhancement of the boron diffusivity by as much as 300 times in the thin gate oxide results in a very shallow exponential p-type profile in the underlying silicon substrate. The effect of fluorine and phosphorus coimplantation into the p-type polysilicon gate is modeled by changes in the boron diffusivity in the gate oxide and segregation at the polysilicon-oxide interface. An inverse PMOS short-channel behavior in which the threshold voltage becomes more negative with decreasing channel length is modeled by two-dimensional boron segregation effects caused by the poly gate oxidation