All-pole phase-locked loops: calculating lock-in range by using Evan's root-locus

The dynamics of a phase-locked loop (PLL), an essential component for the electronic synchronization processes, is described by an ordinary nonlinear differential equation with an order equal to 1 plus the order of its internal linear low-pass filter. Literature contains several results mainly concerned to the second-order loops giving expressions for lock-in range and transient response specifying a linear equivalent second-order system. However, in some applications, more accurate transient responses are necessary and the PLL performance can be improved by considering the higher-order filters resulting in the nonlinear loops with order greater than 2. Such systems, due to high order and nonlinear terms, depending on the parameters combination can present some undesirable behaviors, resulting from bifurcations, as error oscillation and chaos, decreasing the synchronization ranges. Implication to engineering design is that some regions of the parameter space become forbidden limiting the circuit options. This work is a contribution on establishing the lock-in range for a PLL of generic order n?+?1, considering that the filter is all-pole linear stable low-pass of order n. Analysis is performed by detecting a Hopf bifurcation on the synchronous state by using the root-locus method combined with the dynamical system theory. The lock-in range is calculated by applying the classical control tools defining an equivalent feedback control system.     

Analyzing the effect of the phase-jitter in the operation of second order phase-locked loops

Phase-locked loops (PLLs) are designed to extract timing signals in telecommunication networks. Noise, cross-talk, inter-symbol interference, quantization noise, and signal distortion are responsible for oscillations in the time between two successive transitions of the clock or data signal. It appears as an accidental phase modulation superposed to the original signal. This phenomenon is called timing jitter and affects the integrity of the data recovering process and, as a consequence, the error bit rate is increased. This problem has been studied by treating the jitter as a band limited noise process and tolerance masks for the jitter amplitude and frequency are recommended for several network architectures. Here, we develop a simple model with the continuous phase deviations of the clock signals considered as periodic signals in the band of the real disturbances. Comparisons with the stochastic approach are presented.     

Mutually connected phase-locked loop networks: dynamical models and design parameters

Distribution of timing signals is an essential factor for the development of digital systems for telecommunication networks, integrated circuits and manufacturing automation. Originally, this distribution was implemented by using the master?slave architecture with a precise master clock generator sending signals to phaselocked loops (PLL) working as slave oscillators. Nowadays, wireless networks with dynamical connectivity and the increase in size and operation frequency of the integrated circuits suggest that the distribution of clock signals could be more efficient if mutually connected architectures were used. Here, mutually connected PLL networks are studied and conditions for synchronous states existence are analytically derived, depending on individual node parameters and network connectivity, considering that the nodes are nonlinear oscillators with nonlinear coupling conditions. An expression for the network synchronisation frequency is obtained. The lock-in range and the transmission error bounds are analysed providing hints to the design of this kind of clock distribution system.     

Two-way master-slave double-chain networks: limitations imposed by linear master drift for second order PLLs as slave nodes

Distribution of precise time signals among the nodes of a network is a fundamental requirement for digital transmission and switching systems in telecommunication and control. Cideciyan et al., (1987) conjectured that two-way master-slave (TWMS) networks present, in the general case, a better performance than one-way master-slave (OWMS) considering the long term linear master frequency drift. In this work we study the TWMS case using dynamical system theory showing that, due to the effects of long-term clock instabilities, the steady-state frequency-error is unstable for a number of slaves higher or equal than four, limiting the use of this kind of architecture.     

Estimating the critical number of slave nodes in a single-chain PLL network

The existence and stability conditions for the synchronous state in telecommunication networks with single-chain master-slave clock distribution architecture are determined. The slave nodes are modeled as first-order phase-locked loops (PLLs) and the signal processing and propagation delays are taken into account. We analytically show that if the number of slaves exceeds a critical value, synchronization is unreachable.     

Global and partial synchronism in phase-locked loop networks

We analytically investigate the existence of global and partial synchronism in neural networks where each node is represented by a phase oscillator. Partial synchronism, which is important to pattern recognition, can be caused by increasing the natural frequency of an oscillator and restricting the frequencies of others in certain ranges.     

A geometric approach for turbo decoding of reed-solomon codes in QAM modulation schemes

This work studies the turbo decoding of Reed- Solomon codes in QAM modulation schemes for additive white Gaussian noise channels (AWGN) by using a geometric approach. Considering the relations between the Galois field elements of the Reed-Solomon code and the symbols combined with their geometric dispositions in the QAM constellation, a turbo decoding algorithm, based on the work of Chase and Pyndiah, is developed. Simulation results show that the performance achieved is similar to the one obtained with the pragmatic approach with binary decomposition and analysis.     

Computing with phase locked loops: choosing gains and delays

We simulate a four-node fully connected phase-locked loop (PLL) network with an architecture similar to the neural network proposed by Hoppensteadt and Izhikevich (1999, 2000), using second-order PLLs. The idea is to complement their work analyzing some engineering questions like:how the individual gain of the nodes affects the synchronous state of whole network; how the individual gain of the nodes affects the acquisition time of the whole network; how close the free-running frequencies of the nodes need to be in order to the network be able to acquire the synchronous state; how the delays between nodes affect the synchronous state frequency. The computational results show that the Hoppensteadt-Izhikevich network is robust to the variation of these parameters and their effects are described through graphics showing the dependence of the synchronous state frequency and acquisition time with gains, free-running frequencies, and delays.