Implementation of media processors

Conventional standard processors do not correspond well to the characteristics of multimedia signal processor algorithms. Therefore, special architectural approaches are necessary for multimedia processors to deliver the required high processing power with efficient use of hardware resources. Programmable approaches offer a high degree of flexibility. In order to attain multimedia signal processor performance, architectural strategies for programmable processors are based on parallelization and adaptation principles. The future multimedia signal processor implementation hinges upon an optimal trade-off between the two design spaces, which can be effectively addressed by a codesign approach     

VLSI chip set for 2D HDTV subband filtering with on-chip linememories

A chip set for 2D subband filtering of HDTV signals has been designed, fabricated and successfully tested. The two chips perform 10*14 quadrature mirror filtering for analysis filtering at the coder and synthesis filtering at the decoder. In order to achieve a very compact realization, the architectures utilize all a priori known properties of the filter algorithm. A 2D polyphase filter structure reduces the processing clock rate from the 72-MHz sampling rate to a moderate 18 MHz. The memory for vertical filtering is realized by on-chip parallel shift registers with multiphase clocking. A small silicon area for the filter arithmetic is achieved by application of carry save adder trees with fixed filter coefficients represented by canonical signed digits. A complete filterbank for luminance and chrominance signals consists of four identical chips, each with 450 000 transistors on 92 mm²     

Architecture Concepts for Multimedia Signal Processing

Architectural concepts are presented aimed at future multimedia processing schemes. Starting from an analysis of current and future multimedia applications, specific computational requirements are derived. It will be shown that multimedia applications benefit from an exhaustive and flexible exploitation of parallelism. Three architectural concepts—reconfigurable computing, simultaneous multithreading, and associative controlling—are presented, and their potential to increase further the performance on future multimedia applications is investigated.     

A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications

A methodological framework for performance estimation of multimedia signal processing applications on different implementation platforms is presented. The methodology derives a complexity profile which is characteristic for an application, but completely platform-independent. By correlating the complexity profile with platform-specific data, performance estimation results for different platforms are obtained. The methodology is based on a reference software implementation of the targeted application, but is, in constrast to instruction-level profiling-based approaches, fully independent of its optimization degree. The proposed methodology is demonstrated by example of an MPEG-4 Advanced Simple Profile (ASP) video decoder. Performance estimation results are presented for two different platforms, a specialized VLIW media processor and an embedded general-purpose RISC processor, showing a high accuracy of he methodology. The approach can be employed to assist in design decisions in the specification phase of new architectures, in the selection process of a suitable target platform for a multimedia application, or in the optimization stage of a software implementation on a specific platform.Hans-Joachim Stolberg received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.From 1995 to 1996, he worked at the NEC Information Technology Research Laboratories, Kawasaki, Japan, on efficient implementation of video compression algorithms. Since 1996, he has been with the Institute of Microelectronic Systems at the University of Hannover as a Research Assistant. During summer 2001, he was a Monbukagakusho Research Fellow at the Tokyo Institute of Technology, Japan. His current research interests include VLSI architectures for video signal processing, performance estimation of multimedia schemes, and profile-guided memory organization approaches for signal processing and multimedia applications.Mladen Bereković received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.Since then he has been a Research Assistant with the Institute of Microelectronic Systems of the University of Hannover. His current research interests include VLSI architectures for video signal processing, MPEG-4, System-on-Chip (SOC) designs, and simultaneously multi-threaded (SMT) processor architectures.Peter Pirsch received the Ing. grad. degree from the engineering college in Hannover, Germany, in 1966, and the Dipl.-Ing. and Dr.-Ing. degrees from the University of Hannover, in 1973 and 1979, respectively, all in electrical engineering.From 1966 to 1973 he was employed by Telefunken, Hannover, working in the Television Department. He became a Research Assistant at the Department of Electrical Engineering, University of Hannover, in 1973, a Senior Engineer in 1978. During 1979 to 1981 he was on leave, working in the Visual Communications Research Department, Bell Laboratories, Holmdel, NJ. During 1983 to 1986 he was Department Head for Digital Signal Processing at the SEL Research Center, Stuttgart, Germany. Since 1987 he is Professor in the Department of Electrical and Computer Engineering at the University of Hannover. He served as Vice President Research of the University of Hannover from 1998 to 2002.His present research includes architectures and VLSI implementations for image processing applications, rapid prototyping and design automation for DSP applications. He is the author or coauthor of more than 200 technical papers. He has edited a book on VLSI Implementations for Image Communications (Elsevier 1993) and is author of the book Architectures for Digital Signal Processing (John Wiley 1998).Dr. Pirsch is a member of the IEEE, the German Institute of Information Technology Engineers (ITG) and the German Association of Engineers (VDI). He was recipient of several awards: the NTG paper price award (1982), IEEE Fellow (1997), IEEE Circuits and Systems Golden Jubilee Medal (1999). He was member or chair of several technical program committees of international conferences and organizer of special sessions and preconference courses. He has held several administrative and technical positions with the IEEE Circuits and Systems Society and other professional organizations. Dr. Pirsch currently serves as Vice President Publications of the IEEE Circuits and Systems Society. Since 2000 he is chairman of the Accreditation Commission for Engineering and Informatics of the Accreditation Agency for Study Programs in Engineering, Informatics, Natural Science and Mathematics (ASIIN). Dr. Pirsch is chair of the VDI committee on Engineering Education.     

Design and technological solutions for the plasma facing components of WENDELSTEIN 7-X

The operation of W7-X stellarator for pulse length up to 30 min with 10 MW input power requires a full set of actively water-cooled plasma facing components. From the lower thermally loaded area of the wall protection system designed for an averaged load of 100 kW/m² to the higher loaded area of the divertor up to 10 MW/m², various design and technological solutions have been developed meeting the high load requirements and coping with the restricted available space and the particular 3D-shaped geometry of the plasma vessel. 80 ports are dedicated alone to the water-cooling of plasma facing components and a complex networking of kilometers of pipework will be installed in the plasma vessel to connect all components to the cooling system. An advanced technology was developed in collaboration with industry for the target elements of the high heat flux (HHF) divertor, the so-called “bi-layer” technology for the bonding of flat tiles made from CFC NB31 onto the CuCrZr cooling structure. The design, R&D and the adopted technological solutions of plasma facing components are presented. At present, except the HHF divertor, most of plasma facing components has been already manufactured.     

Design analysis and manufacturing of the cooling lines of the in vessel components of WENDELSTEIN 7-X

All in vessel components (IVCs) of W7-X are actively cooled. Inside the plasma vessel about 4 km of pipes will be installed, supplying water to the IVC. 226 cooling circuits with 78 variants are necessary. The cooling circuits enter the cryostat and the plasma vessel through ad hoc flanged penetrations called “plug-ins”, which provide for the vacuum boundary between the plasma chamber and the torus hall atmosphere. The plug-ins are installed inside the W7-X ports. Some of the plug-ins are also used for the diagnostic cables. In total eighty plug-ins will be produced and installed. The inlet/outlet cooling lines are connected to the plug-ins using a welded hydraulic connector. The layout of the cooling lines is rather complex in consideration of the limited space and the routing between many component parts. Additionally the differential thermal expansion of the lines with respect to the supporting structures during the different operation scenarios had to be compensated by ad hoc supports and adjustments in the flexibility of the lines.     

Determinants of graft survival after renal transplantation

We studied multiple determinants of graft survival at a single center and the effects of nonimmunologic graft loss on transplant survival. This retrospective study examined the results of 589 cadaver donor transplants performed between 1986 and 1992. Graft survival rates were calculated using Kaplan-Meier estimates for both overall graft survival (all causes of graft loss) and immunologic graft survival (function lost due to acute or chronic rejection and noncompliance). Cadaver graft survival was significantly poorer with an increasing degree of DR mismatch (P=0.02). An analysis of pretransplant variables showed graft loss risk was highest with greater DR mismatches, two B-antigen mismatch, higher donor serum creatinine, and younger recipient age. After transplantation, acute rejection was the most significant factor associated with long-term graft survival. Our data demonstrate a significant advantage for zero DR and one DR mismatch cadaver donor transplants, with excellent immunologic graft survival. This study suggests that a combination of immediate graft function, prevention of acute rejection by appropriate early immunosuppressive therapy, and acceptable DR match enhances cadaveric graft survival.     

VLSI architectures for video compression-a survey

The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO. VLSI implementation strategies are discussed and split into function specific and programmable architectures. As examples for the function oriented approach, alternative architectures for DCT and block matching will be evaluated. Also dedicated decoder chips are included Programmable video signal processors are classified and specified as homogeneous and heterogenous processor architectures. Architectures are presented for reported design examples from the literature. Heterogenous processors outperform homogeneous processors because of adaptation to the requirements of special, subtasks by dedicated modules. The majority of heterogenous processors incorporate dedicated modules for high performance subtasks of high regularity as DCT and block matching. By normalization to a fictive 1.0 μm CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This relationship indicates a figure of merit for silicon efficiency     

Design of DPCM Quantizers for Video Signals Using Subjective Tests

The application of differential pulse code modulation (DPCM) for broadcast color television signals requires a design which produces no visible impairments under normal viewing conditions. This paper describes a quantizer design which is based on measured visibility thresholds of the various kinds of DPCM impairments such as granular noise, edge busyness, and slope overload. The visibility thresholds are determined by subjective tests based on comparisons of DPCM and PCM encoded pictures. Constructions of quantizers are carried out such that the number of levels is minimized without exceeding the measured visibility thresholds. Besides nonadaptive quantizers, adaptive quantizers are also constructed which are controlled by the signal changes of surrounding picture elements. These investigations show that for component coding of color video signals with two-dimensional prediction, a transmission rate of 31.7 Mbits/s is possible for natural types of test pictures without visible impairments using constant word length coding.